Why is this line getting the error : Expecting a left parenthesis ( '(' ) [12.1.2][7.1(IEEE)]?

Question

I have a Verilog code for a simple multiplier as shown below, which takes two 32-b inputs which are split into two (16-b MSB and 16-b LSB) and multiplied:

parameter WordLen1 = 32, WordLen2 = 16; 
output [WordLen2-1:0] M;
input clk; 
input signed [WordLen1-1:0] X, W1;

reg signed [WordLen1-1 :0] X_reg, W1_reg, M;
wire signed [WordLen2-1:0] mul1, mul2, M_out;

assign mul1 = X_reg[31:16] * W1_reg[31:16]; <--- 16-b MSB
assign mul2 = X_reg[15:0] * W1_reg[15:0]; <--- 16-b LSB
assign M_out = mul1 + mul2;

always@(posedge clk)
begin
    X_reg <= X;
    W1_reg <= W1;
    M <= M_out;
end 
endmodule 

The testbench for the code is below:

Note : The inputs are read from two external text files having 32-b values each.

module testbench;
reg clk;
parameter WL1 = 32, WL2 = 16;
reg  [WL1-1:0] Xinarray [0:1];           // define memory arrays to hold inputs
reg  [WL1-1:0] W1inarray [0:1]; 
logic signed [WL1-1:0] X,W1; <------ Error : Expecting a left parenthesis

endmodule

I am getting the following error in my test bench:

logic signed [WL1-1:0] X,W1;
           |
ncvlog: *E,EXPLPA (../src/mult_hidden_tb.v,9|11): expecting a left parenthesis ('(') [12.1.2][7.1(IEEE)].
logic signed [WL1-1:0] X,W1;
                 |
ncvlog: *E,EXPLPA (../src/mult_hidden_tb.v,9|17): expecting a left parenthesis ('(') [12.1.2][7.1(IEEE)].
logic signed [WL1-1:0] X,W1;
                        |
ncvlog: *E,EXPLPA (../src/mult_hidden_tb.v,9|24): expecting a left parenthesis ('(') [12.1.2][7.1(IEEE)].
logic signed [WL1-1:0] X,W1;
                           |
ncvlog: *E,EXPLPA (../src/mult_hidden_tb.v,9|27): expecting a left parenthesis ('(') [12.1.2][7.1(IEEE)].

I'm not sure what I'm doing wrong.

Answer 1

You need to check ncverilog tool compile the code as system verilog code, not as verilog.

"logic" data type is defined in system verilog. But in Verilog, "logic" is not defined. In Verilog, you can use "wire" or "reg".

So if you want to compile the code as verilog, "logic" must changed into "reg" or "wire".

But then the variable cannot be used in "always"(or "initial") and "assign" together.

In case of input port(you defined X and W1 as input at your top module), you may use "reg" used at "initial" or "always" block.