x86: Instruction reorder related with `cmpxchg` (without lock prefix)?

Question

Could a memory write instruction (mov reg to memory) after cmpxchg (without lock prefix) be recordered and executed before cmpxchg for x86?

EX1:

    // try_cmpxchg_local(&local.pos, &tail, tail + 1)
I1: cmpxchg dword ptr [rsi], edi

    // now the tail-th position is reserved
    // WRITE_ONCE(local.dat, value);
I2: mov qword ptr [r11], r10

The question is: could I2 be reordered before I1? I'm assuming it's a YES since there are no dependencies between I2 and I2. (It's wrong, should be a NO.)

How about other architectures (weak consistency especially)? Need a sfence between I1 and I2 to guarantee the order?

EX2: the actual example in reality will have a conditional branch like this:

    // try_cmpxchg_local(&local.pos, &tail, tail + 1)
I1: cmpxchg dword ptr [rsi], edi
    cmp edx, eax
    jnz ...

    // now the tail-th position is reserved
    // WRITE_ONCE(local.dat, value);
I2: mov qword ptr [r11], r10 

So for EX2, with spectre mitigated, I2 won't happen before I1. Am I right?