I am trying to verify a sMEM design using assertions in systemVerilog however I got a problem I did not Know How to solve it : I am supposed to verify if:
On rising edge of CLKA, when BLKA is 1 and RWA is 1, data is read at ADDRA address of the RAM and the result is available at DOUTA.
in my design the RAM is defined as shared variable
so how can I write assertions ?
An assertion is not something I would use to verify a memory. Assertions are best for verifying protocols, not functionality. And since your memory is likely a vendor macro, theres no need for you to test its internal functionality. You mainly need to test the connectivity to the memory. There are pre-defined tests that involve writes followed by reads for memory verification.