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20
Devhide
2025-01-03 21:20:37
10.2k
Views
`uvm_do_with with inline constraints
Published on
03 January 2025 at 21:20
#system-verilog
#uvm
880
Views
Error - near ":": syntax error, unexpected ':', expecting IDENTIFIER or clock
Published on
03 January 2025 at 21:37
#macros
#system-verilog
#uvm
3.3k
Views
Error - :near "(": syntax error, unexpected '(', expecting IDENTIFIER or '='
Published on
03 January 2025 at 21:34
#macros
#system-verilog
#uvm
4.9k
Views
UVM virtual sequencer: choose the right child sequencer
Published on
03 January 2025 at 21:32
#system-verilog
#uvm
1.8k
Views
UVM blocking assignment race conditions
Published on
03 January 2025 at 21:20
#system-verilog
#uvm
1.1k
Views
Grab Transactions inside UVM_Sequencer Run Phase
Published on
03 January 2025 at 21:28
#system-verilog
#uvm
330
Views
Where does get_and_drive come from?
Published on
03 January 2025 at 21:18
#uvm
1.6k
Views
Is it good idea to declare config object in uvm_sequence_item
Published on
02 January 2025 at 16:45
#verilog
#verification
#system-verilog
#uvm
427
Views
UVM: Does setting values to sequence_item before I call start_item(seq_item) cause any issue?
Published on
02 January 2025 at 16:46
#verilog
#verification
#system-verilog
#uvm
2.9k
Views
How to intercept uvm_error and cause a callback?
Published on
03 January 2025 at 21:28
#system-verilog
#uvm
9.7k
Views
calling $dumpvars() from a task
Published on
03 January 2025 at 21:16
#verilog
#system-verilog
#uvm
1.2k
Views
Can UVM flag a bad command line argument?
Published on
03 January 2025 at 21:20
#command-line-arguments
#system-verilog
#uvm
771
Views
parameterized class queue in sv
Published on
03 January 2025 at 21:16
#system-verilog
#uvm
3k
Views
What is the purpose of register model in UVM?
Published on
03 January 2025 at 21:25
#system-verilog
#uvm
1.1k
Views
What is the purpose of UVM Virtual Sequencers
Published on
03 January 2025 at 21:25
#uvm
7.6k
Views
how to find out the existence of a file in system verilog
Published on
03 January 2025 at 21:33
#unix
#system
#verilog
#system-verilog
#uvm
1.9k
Views
How to synchronize two unrelated UVM sequence items from different UVM agents?
Published on
03 January 2025 at 21:40
#system-verilog
#uvm
1.4k
Views
What is `uvm_field_* macros for time datatype
Published on
03 January 2025 at 21:22
#system-verilog
#uvm
536
Views
Static integer in a class method shows unexpected behaviour
Published on
03 January 2025 at 21:34
#verilog
#system-verilog
#uvm
227
Views
ASIC verification of a multiport switch
Published on
03 January 2025 at 21:20
#system-verilog
#uvm
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