Aldec Active-HDL: vlib in GUI gives "Warning: Cannot create library" without usable library

Question

From the Aldec Active-HDL GUI the vlib should create a work library, e.g.:

vlib my_lib

This creates a "my_lib" directory under the current directory, but with the warning:

Warning: Cannot create library

A subsequent set worklib my_lib fails with error "Error: Design not loaded.", and a compile with vcom -work my_lib tb.vhd completes without output and neither compiles anything to the "my_lib" directory. So it looks like even through a "my_lib" directory is created, it is not made available as "my_lib" library for VHDL compile.

If using the Aldec Active-HDL Command Line Interface (CLI) through vsimsa.bat it works fine.

What is required to make Tcl vlib command work from the GUI Tcl console window?

It probably looks like the problem is that a local "library.cfg" file is not created just by doing vlib my_lib, so in this case, how to create a local "library.cfg" file for simple module compile and simulation?

Answer 1

This might not be the root cause of your problem but I just feel the need to enlighten you about the misuse of work as a library name.

work is really not a valid library name in VHDL. It is also not some kind of pre-defined default library. The VHDL standard defines work as a special alias for the current working library. Thus one can use work inside a VHDL file to reference other design units within the same library without knowing the name of the library into which they will be analyzed. Since work is a special alias it does not need to be referenced with a library work clause before any use work.pkg.all clauses.

Unfortunately many VHDL tools allow a designer create libraries named work, some even encourage it contributing to the confusion. This works fine as long as no design unit in another library tries to reference a design unit within the badly named work library. This is because the work name will be an alias for the other library within the context of files analyzed into that library.

This fact is little known even among experienced VHDL designers. Maybe the root cause of the confusion is that many tools often talk about a "work library" meaning the "current work library whatever it is called" which people interpreted literally to mean it should actually be named work.

Example of work problem:

pkg.vhd

package pkg is
end package;

file.vhd

use work.pkg.all;

Good case

vcom -work lib pkg.vhd
vcom -work lib file.vhd

The files pkg.vhd and file.vhd can be compiled into a library with any name since they use the work alias.

Bad case

vcom -work work pkg.vhd
vcom -work lib file.vhd

There will be an error on the second command since work refers to lib when analyzing file.vhd since the current working library was lib. It is impossible to reference anything in the badly named work library from within lib since all references containing the special alias work will be translated into lib.

Answer 2

It is appears like it is not possible to create a library outside a workspace with design, so this has to be created.

See also the question and answer at https://stackoverflow.com/a/30936868/3989931