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20
1.1k
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Is an inferred latch in Quartus II necessarily transparent

Published on
#vhdl #fpga #synthesis #quartus
249
Views

VHDL, concurrent signal assignment wrong on FPGA but right in Modelsim

Published on
#signals #vhdl #fpga #modelsim
12.1k
Views

Others => '1' statement in Verilog

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#vhdl #verilog
1k
Views

VHDL: Internal signal in component not triggered

Published on
#vhdl #vivado
457
Views

WARNING:Xst:1290 and WARNING:Xst:528

Published on
#vhdl
290
Views

What does it mean whe you have: case state is when vale1 => state <= value2 in vhdl?

Published on
#vhdl
497
Views

Data transfer between fpga (14 bits) vhdl block to NIos II system (16 bits)

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#c #variables #vhdl #transfer #bit
1.4k
Views

How can I merge several Xilinx NGC netlists to an new netlist

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#vhdl #xilinx #synthesis #xilinx-ise #netlist
9.4k
Views

Random Generator using UNIFORM

Published on
#vhdl #uniform
3.8k
Views

Read file in FPGA

Published on
#vhdl #fpga #xilinx
4.8k
Views

VHDL OR logic with 32 bit vector

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#vector #components #vhdl #bit
1.6k
Views

VHDL average of Array through for loop

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#arrays #for-loop #vhdl #moving-average
2.4k
Views

VHDL using two components from a second file

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#components #vhdl #modelsim
1.6k
Views

Multiple behaviours for single entity

Published on
#testing #process #entity #vhdl
26.9k
Views

No feasible entries for infix operator "+"

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#vhdl
2.4k
Views

Passing the (initial) value of a shared variable to a generic during component instantiation

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#vhdl #xilinx #hdl
2.9k
Views

importing VHDL packages to SV from libraries other than WORK

Published on
#vhdl #system-verilog #assertions
5.7k
Views

how to add two 16-bit STD_LOGIC_VECTOR and a carry into 17-bit in VHDL?

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#vhdl
2.5k
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Put attributes into file possible?

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#attributes #vhdl
98
Views

Warning about getting "X"es for 4-valued logic VHDL

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#vhdl

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