"assign" followed by "always" - what is the order of evaluation?

Question

I found the following MAC code in a verilog course and I am not able to make sense of how the MAC unit's earlier output is being fedback to the adder so that it can add this to the multiplier output.

module mult_acc(input data1,data2, clk,aclr,output reg mac_out);
wire mult_out,add_out;
assign add_out = mult_out+mac_out; // dataflow 
multiplier my_mult(.in1(data1),.in2(data2),.out(mult_out))
always(@posedge clk, posedge aclr) 
begin
if(aclr)
mac_out<= 1'b0;
else
mac_out<= add_out;
end
endmodule

In the above code,I have multiple questions

1.Is the feedback relationship defined when at the dataflow definition line ('assign' line). 2. Is the module instantiation my_mult also produce the mult_out output? 3. If the assign statement and mult_out all evaluate concurrently, then how does the assign statement get the newest mult_out value? 4. Is the always block evaluated after the assign and mult_out ?

I am a complete beginner in Verilog, as in I started 3 days ago, so any help is deeply appreciated.

Answer 1

Verilog is a language which describes behavior of hardware.

Hardware is a set of hardware devices connected to each other with wires. All such devices function in parallel. They have inputs and outputs and modify outputs reacting to changes on inputs. It does not matter where and how the devices are located on the chip or board in order to function properly. Only connections matter.

Verilog mimics it using event-driven simulation technique. So, it does not matter where statements and module instantiations are located in the code. As soon as they are connected properly, they will function correctly. Verilog simulator will figure out in which order to execute the statements based on connectivity information.

As an example, if mult_out changes, it will cause execution of the previous assign statement, because mult_out is an input to this statement. As a result it will change add_out. The following always block has two inputs: clk and aclkr. As soon as one of them changes, the block will execute. The value of add_out will be used to modify mac_out which will trigger execution of the assign statement again (if changed), and so on.