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20
Devhide
2025-01-03 02:52:06
467
Views
vhdl package signals modelsim wlf
Published on
03 January 2025 at 02:52
#vhdl
#modelsim
#vlsi
151
Views
What will be the circuit for the counter with oscillating 1s (1000, 0100, 0010, 0001, 0010, 0100)?
Published on
02 January 2025 at 23:43
#verilog
#counter
#circuit
#vlsi
7.7k
Views
VHDL internal signal to change output - not working?
Published on
03 January 2025 at 02:56
#output
#vhdl
#fsm
#vlsi
356
Views
Microwind does not create my equation in compile
Published on
03 January 2025 at 02:56
#layer
#mask
#vlsi
1.4k
Views
How can i catch error message from command line TCL
Published on
03 January 2025 at 03:54
#try-catch
#tcl
#message
#qsub
#vlsi
109
Views
Filter out pins having same clock attribute
Published on
01 January 2025 at 14:26
#tcl
#filtering
#vlsi
#cadence
#searchfiltercollection
101
Views
Error in the code I am unable to solve it and i am unable to prevent the error
Published on
03 January 2025 at 03:05
#verilog
#system
#vlsi
83
Views
Convert lef-def layout to gds using klayout
Published on
07 January 2025 at 13:13
#ruby
#vlsi
#stacklayout
#docklayoutpanel
70
Views
Expecting a SInt value from a Wire, in Chisel
Published on
02 January 2025 at 20:50
#scala
#chisel
#circuit
#vlsi
#chiseltest
581
Views
What's the difference between `transaction and `transaction`event in VHDL
Published on
01 January 2025 at 17:10
#vhdl
#register-transfer-level
#vlsi
198
Views
Efficient Signed Multiplier with good timing
Published on
03 January 2025 at 02:55
#vhdl
#pipeline
#fpga
#vlsi
3.4k
Views
What is the difference between begin end and fork join with respect to non-blocking statements?
Published on
03 January 2025 at 03:07
#verilog
#system-verilog
#fork-join
#vlsi
363
Views
How do I communicate multiple ARINC429 channels with SPI slave device in VHDL
Published on
03 January 2025 at 03:04
#vhdl
#spi
#vlsi
53
Views
Scaling delay values in Design compiler topographical
Published on
03 January 2025 at 02:58
#vlsi
1.5k
Views
k-Nearest Neighbour Algorithm in verilog
Published on
03 January 2025 at 02:53
#verilog
#fpga
#knn
#euclidean-distance
#vlsi
63
Views
theoretical calculations of delay of a logic gate of 45 nm technology
Published on
03 January 2025 at 03:03
#vhdl
#xilinx
#vlsi
250
Views
Does adding buffer in a digital path increase the delay or reduce the delay and why?
Published on
03 January 2025 at 03:06
#digital
#vlsi
106
Views
"assign" followed by "always" - what is the order of evaluation?
Published on
03 January 2025 at 03:00
#verilog
#system-verilog
#vlsi
29
Views
How are current generation clock frequencies achieved?
Published on
03 January 2025 at 02:58
#clock
#adc
#vlsi
415
Views
Does SystemVerilog Generate support delays?
Published on
03 January 2025 at 02:54
#verilog
#system-verilog
#test-bench
#vlsi
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