Chisel randomly initialize register value when simulating with verilator

Question

I'm using Chisel and blackbox to run my chisel logic against a verilog register file. The registerfile does not have reset signal so I expect the register to be randomly initialized.

I passed the --x-initial unique to verilator, Basically this is how I launch the test:

  private val backendName = "verilator"

  "NOCDMA" should s" do blkwrite and blkread correctly (with $backendName)" in {
    Driver.execute(Array("--fint-write-vcd","--backend-name",s"$backendName",
      "--more-vcs-flags","--trace-depth 1 --x-initial unique"),
      ()=>new DMANetworkWithMem(memAddrWidth,memDataWidth)(nocDataWidth)(nNodesX,nNodesY)){
      c => new DMANetworkRWTest(c)
    }
  }

But The data I read from the register file is all zero before I wrote anything to it.

The read data is correct after I wrote to it.

So, is there anything inside chisel that I need to tune or I did not do everything properly ?

Any suggestions?

Answer 1

I'm not certain, but I found the following issue on Verilator with a similar issue: https://github.com/verilator/verilator/issues/1399.

From skimming the above issue, I think you also need to pass +verilator+seed+<value> and +verilator+rand+reset+<value> at runtime. I am not an expert in the iotesters, but I believe you can add these runtime values through the iotesters argument: --more-vcs-c-flags.

Side note, I would also set --x-assign unique in Verilator if there are cases in the Verilog where runtime would otherwise inject an X (eg. out-of-bounds index).

I hope this helps!