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20
Devhide
2024-12-31 09:11:09
359
Views
Verilog/SystemVerilog: "constant" function is considered non-constant
Published on
31 December 2024 at 09:11
#verilog
#system-verilog
#hdl
#yosys
#verilator
119
Views
Using Verilator with CMake when RTL uses a SV package
Published on
31 December 2024 at 09:09
#cmake
#verilator
656
Views
Multithreaded simulation orders of magnitude slower than single-threaded
Published on
31 December 2024 at 09:12
#c++
#multithreading
#performance
#verilator
687
Views
Verilator - explanation of VerilatedVcdC->dump()
Published on
31 December 2024 at 09:07
#verilator
321
Views
Verilog - bitstream works on hardware but simulation doesn't compile
Published on
31 December 2024 at 09:11
#verilog
#verilator
931
Views
How to tell verilator linter to not verify submodule?
Published on
31 December 2024 at 09:09
#verilog
#verilator
305
Views
How to know which simulator is used in cocotb testbench?
Published on
03 January 2025 at 15:13
#python
#verilog
#icarus
#cocotb
#verilator
737
Views
Timescale missing on the module as other modules have it Verilator error
Published on
31 December 2024 at 09:12
#scala
#chisel
#rocket-chip
#verilator
567
Views
How to use Xilinx IP(or primitives) in verilator simulation
Published on
31 December 2024 at 09:10
#verilator
1k
Views
make run for RISC-V Rocket chip emulator fails
Published on
31 December 2024 at 09:08
#riscv
#rocket-chip
#verilator
327
Views
non-hermetic Bazel action to enable remote caching
Published on
31 December 2024 at 09:09
#build
#bazel
#verilator
448
Views
How to convert large Chisel design to C++ model with Verilator?
Published on
31 December 2024 at 09:11
#riscv
#chisel
#verilator
497
Views
Chisel randomly initialize register value when simulating with verilator
Published on
31 December 2024 at 09:12
#chisel
#verilator
216
Views
VERILATOR: Terminal stuck after execution of helloworld SystemVerilog, with C++ wrapper
Published on
02 January 2025 at 17:06
#c++
#verilator
378
Views
Using typedef void* within a .dll
Published on
31 December 2024 at 09:05
#c++
#verilator
292
Views
Dynamic test harness in chisel 3
Published on
31 December 2024 at 09:07
#scala
#automated-tests
#chisel
#verilator
276
Views
How to read memory value at a specific location using VPI and verilator?
Published on
31 December 2024 at 09:12
#verilog
#simulation
#system-verilog
#verilator
#vpi
302
Views
Is it possible to access the member of a user-defined struct in SystemVerilog using VPI and verilator?
Published on
31 December 2024 at 09:13
#verilog
#simulation
#system-verilog
#verilator
432
Views
SystemVerilog Dataflow Modeling Ripple-Adder with array instances
Published on
31 December 2024 at 09:11
#system-verilog
#verilator
421
Views
Verilog: simulation gives errors but runs fine on FPGA
Published on
31 December 2024 at 09:09
#verilog
#simulation
#verilator
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