Question

Verilog/SystemVerilog: "constant" function is considered non-constant

score 311 · Answer 1 · 2023-12-02 19:41:59

311

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Verilog/SystemVerilog: "constant" function is considered non-constant

Published on 02 December 2023 at 19:41

score 83 · Answer 2 · 2023-12-01 13:01:04

83

Views

Using Verilator with CMake when RTL uses a SV package

Published on 01 December 2023 at 13:01

score 616 · Answer 3 · 2021-04-30 14:17:41

616

Views

Multithreaded simulation orders of magnitude slower than single-threaded

Published on 30 April 2021 at 14:17

score 648 · Answer 4 · 2021-05-05 13:19:01

648

Views

Verilator - explanation of VerilatedVcdC->dump()

Published on 05 May 2021 at 13:19

score 280 · Answer 5 · 2021-05-07 11:56:51

280

Views

Verilog - bitstream works on hardware but simulation doesn't compile

Published on 07 May 2021 at 11:56

score 883 · Answer 6 · 2018-11-21 15:45:27

883

Views

How to tell verilator linter to not verify submodule?

Published on 21 November 2018 at 15:45

score 253 · Answer 7 · 2020-07-31 05:38:05

253

Views

How to know which simulator is used in cocotb testbench?

Published on 31 July 2020 at 05:38

score 693 · Answer 8 · 2022-03-19 01:18:23

693

Views

Timescale missing on the module as other modules have it Verilator error

Published on 19 March 2022 at 01:18

score 528 · Answer 9 · 2022-03-27 08:36:41

528

Views

How to use Xilinx IP(or primitives) in verilator simulation

Published on 27 March 2022 at 08:36

score 1k · Answer 10 · 2020-04-11 20:39:29

1k

Views

make run for RISC-V Rocket chip emulator fails

Published on 11 April 2020 at 20:39

score 314 · Answer 11 · 2019-12-12 23:49:15

314

Views

non-hermetic Bazel action to enable remote caching

Published on 12 December 2019 at 23:49

score 433 · Answer 12 · 2019-12-13 13:02:20

433

Views

How to convert large Chisel design to C++ model with Verilator?

Published on 13 December 2019 at 13:02

score 484 · Answer 13 · 2019-12-27 03:47:28

484

Views

Chisel randomly initialize register value when simulating with verilator

Published on 27 December 2019 at 03:47

score 202 · Answer 14 · 2021-08-28 18:47:47

202

Views

VERILATOR: Terminal stuck after execution of helloworld SystemVerilog, with C++ wrapper

Published on 28 August 2021 at 18:47

score 364 · Answer 15 · 2021-03-11 09:43:30

364

Views

Using typedef void* within a .dll

Published on 11 March 2021 at 09:43

score 276 · Answer 16 · 2017-01-12 11:44:26

276

Views

Dynamic test harness in chisel 3

Published on 12 January 2017 at 11:44

score 262 · Answer 17 · 2023-07-20 22:20:18

262

Views

How to read memory value at a specific location using VPI and verilator?

Published on 20 July 2023 at 22:20

score 284 · Answer 18 · 2023-08-01 22:01:45

284

Views

Is it possible to access the member of a user-defined struct in SystemVerilog using VPI and verilator?

Published on 01 August 2023 at 22:01

score 419 · Answer 19 · 2021-12-03 05:55:37

419

Views

SystemVerilog Dataflow Modeling Ripple-Adder with array instances

Published on 03 December 2021 at 05:55

score 407 · Answer 20 · 2021-12-08 15:01:26

407

Views

Verilog: simulation gives errors but runs fine on FPGA

Published on 08 December 2021 at 15:01

List Question

Verilog/SystemVerilog: "constant" function is considered non-constant

Using Verilator with CMake when RTL uses a SV package

Multithreaded simulation orders of magnitude slower than single-threaded

Verilator - explanation of VerilatedVcdC->dump()

Verilog - bitstream works on hardware but simulation doesn't compile

How to tell verilator linter to not verify submodule?

How to know which simulator is used in cocotb testbench?

Timescale missing on the module as other modules have it Verilator error

How to use Xilinx IP(or primitives) in verilator simulation

make run for RISC-V Rocket chip emulator fails

non-hermetic Bazel action to enable remote caching

How to convert large Chisel design to C++ model with Verilator?

Chisel randomly initialize register value when simulating with verilator

VERILATOR: Terminal stuck after execution of helloworld SystemVerilog, with C++ wrapper

Using typedef void* within a .dll

Dynamic test harness in chisel 3

How to read memory value at a specific location using VPI and verilator?

Is it possible to access the member of a user-defined struct in SystemVerilog using VPI and verilator?

SystemVerilog Dataflow Modeling Ripple-Adder with array instances

Verilog: simulation gives errors but runs fine on FPGA

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