cocotb syntax which is equivalent to a unpacked System verilog array

Question

I am working on writing cocotb code for a SV transaction class and I have run into an issue where I am not sure how to declare below random unpacked system verilog array in cocotb.

rand bit [15:0] data[4];

I am thinking of below code but not sure if its right. I am not a point where I can test this. Any suggestions would be helpful.

class some_trans(uvm_sequence_item):
    def __init__(self):
        p = constraint.Problem()
        p.addVariable('data', [range(0, 0x8000), range(0, 0x8000), range(0, 0x8000), range(0, 0x8000)])

I tried below

class some_trans(uvm_sequence_item):
    def __init__(self):
        p = constraint.Problem()
        p.addVariable('data', [range(0, 0x8000), range(0, 0x8000), range(0, 0x8000), range(0, 0x8000)])