Communication to parallel (not cascade) 74hc595 over common bus lines

Question

I am trying to send data to parallel (not cascade) 74hc595 over common bus lines from CD4094B. I am sending 16 bits to place first 8 bits in 74hc595(1) and second bits in 74hc595(2). But I am getting same 8 bits (10101010) on both 74hc595 devices.

How to send 16 bits such that first 8 bits should place in first 74hc595 and second 8 bits should place in second 74hc595?

Code:

uint8_t test[16] = {1,1,1,1,0,0,0,0,1,0,1,0,1,0,1,0};

HAL_GPIO_WritePin(GPIOB, GPIO_PIN_11, GPIO_PIN_SET); // CD4094 OE

for (int bit=0; bit<16; bit++)
{

   HAL_GPIO_WritePin(GPIOB, GPIO_PIN_10, GPIO_PIN_RESET);  //CD4094 STROBE

   output = test[bit] & 1;

   if (output) {

       HAL_GPIO_WritePin(GPIOB, GPIO_PIN_2, GPIO_PIN_SET); //CD4094 DATA

   } else {

       HAL_GPIO_WritePin(GPIOB, GPIO_PIN_2, GPIO_PIN_RESET); //CD4094 DATA 
   }

   HAL_GPIO_WritePin(GPIOB, GPIO_PIN_0, GPIO_PIN_RESET); //CD4094 CLOCK

   HAL_GPIO_WritePin(GPIOB, GPIO_PIN_0, GPIO_PIN_SET);  

   HAL_GPIO_WritePin(GPIOB, GPIO_PIN_10, GPIO_PIN_SET); // CD4094 STROBE

   HAL_GPIO_WritePin(GPIOB, GPIO_PIN_12, GPIO_PIN_RESET); // 74hc595 CLOCK

   HAL_GPIO_WritePin(GPIOB, GPIO_PIN_12, GPIO_PIN_SET);  

}

HAL_GPIO_WritePin(GPIOB, GPIO_PIN_1, GPIO_PIN_RESET); // 74hc595 OE

HAL_Delay(3000);

HAL_GPIO_WritePin(GPIOB, GPIO_PIN_1, GPIO_PIN_SET);

HAL_Delay(3000);

PCB Schematic

Answer 1

I think the problem may be caused by the clock period applied to the CD4094 IC. The time t₁ is probably equal to the processor's clock frequency. The time t₂ is equal to an iterative but uncontrolled time in the for loop. Examine the CD4094's datasheet to see if the appropriate clock period is maintained during data exchange. If the processor clock frequency is high, give a waiting time for the test between the lines I specified below.

HAL_GPIO_WritePin(GPIOB, GPIO_PIN_0, GPIO_PIN_RESET); // CD4094:CLOCK > LOW
/* appropriate delay time should be added to this line */
HAL_GPIO_WritePin(GPIOB, GPIO_PIN_0, GPIO_PIN_SET);   // CD4094:CLOCK > HIGH

NOTE: The third table in the datasheet describes the clock characteristic.

References

• CD4094, CMOS 8-Stage Shift-And-Store Bus Register