CRC implementation in Hardware for multi-bit data

Question

I understand there are free generators available online but I want to understand how the CRC is generated for multi-bit data. I wish to understand how the unfolding of logic works the moment we start taking parallel input bits into consideration. It is easy to understand the serial implementation but I need to understand the logic behind parallel implementation.

Answer 1

Software typically uses a table lookup to process multiple bits at a time, such as a 256 entry table to process 8 bits at a time, or can use a carryless multiply (like X86 PCLMULQDQ) instruction for CRC.

For hardware, a binary (GF(2)) matrix multiply by a fixed matrix is typically used to replace a table lookup since it takes fewer gates. For example, instead of a 256 x 32 bit lookup table to convert 8 bits of input into a 32 bit crc, the encoding matrix would be an 8 x 32 bit matrix. Matrix multiply would be data[1][8] · encode[8][32] = crc[1][32].