Error (10818): Can't infer register for "E" at clk200Hz.vhd(29) because it does not hold its value outside the clock edge

Question

Im beginner with VHDL. I wanna make a divider that divide clk in by 2 whitch is as output F and F divided by 2 should be E. It always when I want to compile the code show me this error: Error (10818): Can't infer register for "E" at clk200Hz.vhd(29) because it does not hold its value outside the clock edge

Thanks for help

frequency_divider: process (reset, clk_in) begin
        if (reset = '1') then
            F <= '0';
                E <= '0';
            counter <= 0;
        else
                if rising_edge(clk_in) then
                    if (counter = 2) then
                        F <= NOT(F);
                        counter <= 0;
                    else
                        counter <= counter + 1;
                    end if;
                else
                E<=NOT(E);
                end if;
            end if;
    end process;

Answer 1

You are trying to assign a new value to E at all instants in time when there is not a rising edge on the clock (ignoring reset for the moment) and you haven't specified what happens to E when there is a rising edge on the clock. When the reset is not asserted it looks like E should toggle back and forth as fast as possible, except maybe something else should happen on a clock edge. I can't imagine what kind of behavior you really want and neither can the compiler.

If you want an edge-triggered flip-flop, the assignment to that signal must be within a conditional statement that is triggered by a rising_edge() or falling_edge(). An else clause to such a conditional doesn't make much sense for code you intend to synthesize.

You are making this much more complicated then it needs to be. I suggest that you run a simulation and observe the individual bits in counter.

Answer 2

Actually the compiler message is very accurate: your assignment E <= not E is outside the if clause where you check the clock's rising edge. Try moving that assignment up one line, and get rid of the empty else clause.

Answer 3

Reason for the error is describe in Ricks answer.

To reduce your design you may skip counter for generating F, and simply use E to hold the additional state required for division of E by 2. Joe Hass hints this in the last comment of his answer:

frequency_divider : process (reset, clk_in)
begin
  if (reset = '1') then
    F <= '0';
    E <= '0';
  elsif rising_edge(clk_in) then
    E <= not E;
    F <= (not F) when (E = '1') else F;
  end if;
end process;