FIFO with 2 clocks in VHDL

Question

I have a problem with a vhdl assignment. I need to create a FIFO buffer between a bus of 500MHz and another bus of 30MHz.

I have designed a basic FIFO buffer with

inputs: Data_in, Write_EN, CLK_500, Read_EN, CLK_30, FlushFIFO.

outputs: Data_out, FULL, EMPTY.

This buffer was designed using a 2D array:

type fifo_arr is array (0 to 63) of std_logic_vector(39 downto 0);
signal FIFO : fifo_arr := (others => (others => '0'));

The problem is the following: How should I write the processes and maintain a pointer between them for synchronization? With the method that I have tried, the code will not synthesize (ERROR:XST:827 Signal ptr cannot be synthesized)

Any ideas?

thanks and regards

Answer 1

You can find here a pdf of the GitHub project while you can use this link for the entire project.

Another nice project can be found following this link.

Answer 2

It might be an idea to show us the code that it actually complained about!

FIFOs across clock domains are tricky, not to be attempted lightly...

Having said that - as it looks like a homework assignment, a good read can be found here:

http://eda.ee.nctu.edu.tw/jdhuang/courses/ipcd04/paper/alfke_final.pdf

(one of the authors is the late, great, Peter Alfke - he designed the first FIFO chip, in 1969, and is widely regarded as a, or even the, FIFO-guru)

Answer 3

I think you will need a read pointer and write pointer that are both modulo 64, so that the fifo is basically a circular buffer. Use grey coding for the addressing, as grey coded numbers only change 1 bit between adjacent values. This can be used for error checking. Read pointer is on read domain, write pointer is on write domain. Perhaps cross each pointer onto the opposite domain for full and empty checks?

Answer 4

You may have a look into these FIFO cores available a opencores specially the dual clock version of fifo. It would give you a fair idea of synchronizing the pointers

http://opencores.org/project,generic_fifos