For loops and rom in vhdl

Question

I'm doing a musicbox with VHDL. I first played just A4 and I was successful.

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.NUMERIC_STD.ALL;


library UNISIM;

use UNISIM.VComponents.all;


entity Basic is

    Port(   clk : in STD_LOGIC;
        note : out STD_LOGIC;
        );
end Basic;

architecture Behavioral of Basic is

    signal count : unsigned (15 downto 0) := (others => '0');
begin

    note <= std_logic(count(15));
    process (clk)
    begin
        if rising_edge(clk) then
            if (count=56817) then
                count <= "0000000000000000";
            else
                count <= count + 1;
            end if;
            end if;
    end process;
end Behavioral;

My unfinished code is like this

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

library UNISIM;
use UNISIM.VComponents.all;

entity Basic is

    Port(   clk : in STD_LOGIC;
            note : out STD_LOGIC;
            address: in integer range 0 to 31
        );
end Basic;

architecture Behavioral of Basic is

    signal count : unsigned (15 downto 0) := (others => '0');
    signal reg_address : integer range 0 to 31 ;
    type rom_array is array (0 to 31) of integer (4 downto 0);
    constant rom: rom_array := (    "11011", "11011",
                    "11011", "11011","11011", "11011",
                    "11011", "11011", "11011", "11011",
                    "11011", "11011","11011", "11011",
                    "11011", "11011","11011", "11011",
                    "11011", "11011","11011", "11011",
                    "11011", "11011","11011", "11011",
                    "11011", "11011","11011", "11011",
                    "11011", "11011");
begin

    note <= std_logic(count(15));
    process (clk)
    begin
            if rising_edge(clk) then
                reg_address <= address;
                if (reg_address < 32) then
                    if (count = rom(reg_address)) then
                        count <= "0000000000000000";
                    else
                        count <= count + 1;
                    end if;
                else
                    reg_address <= "00000";
                end if;
            end if;
            reg_address <= reg_address + 1;
    end process;
end Behavioral;

the rom values are going to change. I'm trying to generate a sound by dividing the clock. Like 25mhz/56818 = 440. To play a song I thought of creating a rom filled with numbers needed to divide the clock, then do a for loop and play the song. But I can't because for loop isn't similar to java/C so I think I need to bypass it.

My errors are:

ERROR:HDLParsers:526 - "C:/Users/user/DigitalProje/Basic.vhd" Line 18. Non array type integer can not have a index constraint.

ERROR:HDLParsers:3312 - "C:/Users/user/DigitalProje/Basic.vhd" Line 19. Undefined symbol 'rom_array'.

ERROR:HDLParsers:1209 - "C:/Users/user/DigitalProje/Basic.vhd" Line 19. rom_array: Undefined symbol (last report in this block)

ERROR:HDLParsers:3285 - "C:/Users/user/DigitalProje/Basic.vhd" Line 19. No array or record type can be found that has elements of types matching the aggregate.

ERROR:HDLParsers:532 - "C:/Users/user/DigitalProje/Basic.vhd" Line 19. Deferred constant are allowed only in packages.

ERROR:HDLParsers:808 - "C:/Users/user/DigitalProje/Basic.vhd" Line 35. = can not have such operands in this context.

ERROR:HDLParsers:800 - "C:/Users/user/DigitalProje/Basic.vhd" Line 41. Type of reg_address is incompatible with type of 00000.

Answer 1

VHDL is a strong-typed language, so you must be strict with the types.

Two issues, the rom_array is made with integer type elements, but it looks like the intention may have been to use unsigned (or another vector type) based on the constant assign to rom; so maybe do:

type rom_array is array (0 to 31) of unsigned (4 downto 0);

The reg_address is integer, thus it can't be assigned with string like in reg_address <= "00000";, so consider changing this to:

reg_address <= 0;