Question

Run AVX SIMD instruction in VScode on Windows with a WSL

score 57 · Answer 1 · 2024-02-21T19:38:09.037000

57

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Run AVX SIMD instruction in VScode on Windows with a WSL

Published on 21 February 2024 at 19:38

score 147 · Answer 2 · 2022-06-06T11:12:12.013000

147

Views

What does this PPC assembly listing do, using lwz from 0(r12) and 4(r12) before a BCTR indirect jump?

Published on 06 June 2022 at 11:12

score 93 · Answer 3 · 2022-04-21T12:34:48.547000

93

Views

How to add an immediate to a VSX register in open power ISA?

Published on 21 April 2022 at 12:34

score 110 · Answer 4 · 2022-03-22T15:25:20.070000

110

Views

Altivec vec_all_gt equivalent on arm neon

Published on 22 March 2022 at 15:25

score 222 · Answer 5 · 2021-10-12T09:57:30.780000

222

Views

Compilation error using AltiVec SIMD vector type in C++

Published on 12 October 2021 at 09:57

score 480 · Answer 6 · 2021-02-14T13:28:31.203000

480

Views

SIMD extensions on power: compiler flags and processor support

Published on 14 February 2021 at 13:28

score 754 · Answer 7 · 2019-07-18T09:57:14.037000

754

Views

Check that at least 1 element is true in each of multiple vectors of compare results - horizontal OR then AND

Published on 18 July 2019 at 09:57

score 826 · Answer 8 · 2018-11-26T11:04:10.590000

826

Views

Error: matching constraint not valid in output operand

Published on 26 November 2018 at 11:04

score 237 · Answer 9 · 2018-11-26T07:12:35.210000

237

Views

Clang equivalent of GCC's __builtin_darn()

Published on 26 November 2018 at 07:12

score 1.7k · Answer 10 · 2018-11-01T14:56:42.573000

1.7k

Views

Error: operand out of range (64 is not between 0 and 31)

Published on 01 November 2018 at 14:56

score 90 · Answer 11 · 2018-10-03T18:03:22.867000

90

Views

will 32-bit altivec code work on 64-bit machine

Published on 03 October 2018 at 18:03

score 136 · Answer 12 · 2018-08-05T08:53:54.983000

136

Views

"-qaltivec" is not compatible with "-qarch=pwr5"

Published on 05 August 2018 at 08:53

score 152 · Answer 13 · 2018-03-16T16:07:52.347000

152

Views

How to initialize a AltiVec register from scalars without using compound literals

Published on 16 March 2018 at 16:07

score 169 · Answer 14 · 2018-03-07T20:10:21.370000

169

Views

Why doesn't the compiler fold xxswapd and vperm?

Published on 07 March 2018 at 20:10

score 101 · Answer 15 · 2017-12-12T14:50:38.247000

101

Views

Double-word vector rotates on old Altivec's without 64-bit data type

Published on 12 December 2017 at 14:50

score 350 · Answer 16 · 2017-12-12T11:38:36.403000

350

Views

What is the availability of 'vector long long'?

Published on 12 December 2017 at 11:38

score 163 · Answer 17 · 2017-10-13T02:54:20.613000

163

Views

Does IBM XL/C signal Altivec support in the preprocessor?

Published on 13 October 2017 at 02:54

score 2.9k · Answer 18 · 2017-09-21T10:46:20.673000

2.9k

Views

Is vec_sld endian sensitive?

Published on 21 September 2017 at 10:46

score 442 · Answer 19 · 2017-09-21T01:31:26.270000

442

Views

How to print a vector variable as its 128-bit vsx value?

Published on 21 September 2017 at 01:31

score 141 · Answer 20 · 2017-09-15T09:34:03.910000

141

Views

Power8 vsldoi built-in or replacement

Published on 15 September 2017 at 09:34

List Question

Run AVX SIMD instruction in VScode on Windows with a WSL

What does this PPC assembly listing do, using lwz from 0(r12) and 4(r12) before a BCTR indirect jump?

How to add an immediate to a VSX register in open power ISA?

Altivec vec_all_gt equivalent on arm neon

Compilation error using AltiVec SIMD vector type in C++

SIMD extensions on power: compiler flags and processor support

Check that at least 1 element is true in each of multiple vectors of compare results - horizontal OR then AND

Error: matching constraint not valid in output operand

Clang equivalent of GCC's __builtin_darn()

Error: operand out of range (64 is not between 0 and 31)

will 32-bit altivec code work on 64-bit machine

"-qaltivec" is not compatible with "-qarch=pwr5"

How to initialize a AltiVec register from scalars without using compound literals

Why doesn't the compiler fold xxswapd and vperm?

Double-word vector rotates on old Altivec's without 64-bit data type

What is the availability of 'vector long long'?

Does IBM XL/C signal Altivec support in the preprocessor?

Is vec_sld endian sensitive?

How to print a vector variable as its 128-bit vsx value?

Power8 vsldoi built-in or replacement

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