Question

Why is the standard C# event invocation pattern thread-safe without a memory barrier or cache invalidation? What about similar code?

score 928 · Answer 1 · 2024-12-29 06:08:36

928

Views

Why is the standard C# event invocation pattern thread-safe without a memory barrier or cache invalidation? What about similar code?

Published on 29 December 2024 at 06:08

score 743 · Answer 2 · 2024-12-29 06:04:51

743

Views

Does C++11 guarantee memory ordering between a release fence and a consume operation?

Published on 29 December 2024 at 06:04

score 4.5k · Answer 3 · 2025-01-02 02:17:16

4.5k

Views

Memory barriers force cache coherency?

Published on 02 January 2025 at 02:17

score 258 · Answer 4 · 2025-01-02 02:17:41

258

Views

Spin locked stack and memory barriers (C++)

Published on 02 January 2025 at 02:17

score 567 · Answer 5 · 2025-01-02 02:23:49

567

Views

Lock-free stack: visibility issue when checking hazard pointers during pop()?

Published on 02 January 2025 at 02:23

score 406 · Answer 6 · 2025-01-02 02:19:20

406

Views

Is deadlock possible in this simple scenario?

Published on 02 January 2025 at 02:19

score 391 · Answer 7 · 2025-01-02 02:16:39

391

Views

Are memory fences required here?

Published on 02 January 2025 at 02:16

score 490 · Answer 8 · 2025-01-02 02:25:11

490

Views

lock-free synchronization, fences and memory order (store operation with acquire semantics)

Published on 02 January 2025 at 02:25

score 222 · Answer 9 · 2025-01-02 02:18:59

222

Views

C Variable Not Updating on Thread Iteration

Published on 02 January 2025 at 02:18

score 849 · Answer 10 · 2025-01-02 02:23:39

849

Views

Do I need to use volatile keyword for memory access in critical section?

Published on 02 January 2025 at 02:23

score 245 · Answer 11 · 2025-01-02 02:19:19

245

Views

Does Sleep not have synchronization semantic?

Published on 02 January 2025 at 02:19

score 2.3k · Answer 12 · 2025-01-02 02:22:43

2.3k

Views

What is the impact SFENCE and LFENCE to caches of neighboring cores?

Published on 02 January 2025 at 02:22

score 22k · Answer 13 · 2025-01-02 02:24:08

22k

Views

Does it make any sense to use the LFENCE instruction on x86/x86_64 processors?

Published on 02 January 2025 at 02:24

score 337 · Answer 14 · 2025-01-02 02:21:27

337

Views

Determining the location for the usage of barriers (fences)

Published on 02 January 2025 at 02:21

score 1.3k · Answer 15 · 2024-12-25 03:33:00

1.3k

Views

Memory barriers and Linux kernel spinlock on TILE-Gx

Published on 25 December 2024 at 03:33

score 484 · Answer 16 · 2025-01-02 02:18:58

484

Views

Why don't we need volatile with StampedLock?

Published on 02 January 2025 at 02:18

score 518 · Answer 17 · 2024-12-29 05:51:16

518

Views

Is the example in the membarrier man page pointless in x86?

Published on 29 December 2024 at 05:51

score 779 · Answer 18 · 2025-01-02 02:17:40

779

Views

How to implement a atomic operation?

Published on 02 January 2025 at 02:17

score 3.4k · Answer 19 · 2024-12-29 05:36:15

3.4k

Views

sequentially-consistent atomic load on x86

Published on 29 December 2024 at 05:36

score 207 · Answer 20 · 2025-01-02 02:19:19

207

Views

Full memory barrier and ExclusiveReceiverGroup

Published on 02 January 2025 at 02:19

List Question

Why is the standard C# event invocation pattern thread-safe without a memory barrier or cache invalidation? What about similar code?

Does C++11 guarantee memory ordering between a release fence and a consume operation?

Memory barriers force cache coherency?

Spin locked stack and memory barriers (C++)

Lock-free stack: visibility issue when checking hazard pointers during pop()?

Is deadlock possible in this simple scenario?

Are memory fences required here?

lock-free synchronization, fences and memory order (store operation with acquire semantics)

C Variable Not Updating on Thread Iteration

Do I need to use volatile keyword for memory access in critical section?

Does Sleep not have synchronization semantic?

What is the impact SFENCE and LFENCE to caches of neighboring cores?

Does it make any sense to use the LFENCE instruction on x86/x86_64 processors?

Determining the location for the usage of barriers (fences)

Memory barriers and Linux kernel spinlock on TILE-Gx

Why don't we need volatile with StampedLock?

Is the example in the membarrier man page pointless in x86?

How to implement a atomic operation?

sequentially-consistent atomic load on x86

Full memory barrier and ExclusiveReceiverGroup

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