Question

Why is the standard C# event invocation pattern thread-safe without a memory barrier or cache invalidation? What about similar code?

score 878 · Answer 1 · 2015-06-10 14:48:37

878

Views

Why is the standard C# event invocation pattern thread-safe without a memory barrier or cache invalidation? What about similar code?

Published on 10 June 2015 at 14:48

score 699 · Answer 2 · 2015-06-20 07:57:23

699

Views

Does C++11 guarantee memory ordering between a release fence and a consume operation?

Published on 20 June 2015 at 07:57

score 4.4k · Answer 3 · 2015-06-20 20:05:09

4.4k

Views

Memory barriers force cache coherency?

Published on 20 June 2015 at 20:05

score 212 · Answer 4 · 2015-06-21 09:33:57

212

Views

Spin locked stack and memory barriers (C++)

Published on 21 June 2015 at 09:33

score 526 · Answer 5 · 2016-12-22 22:24:21

526

Views

Lock-free stack: visibility issue when checking hazard pointers during pop()?

Published on 22 December 2016 at 22:24

score 364 · Answer 6 · 2016-12-27 07:33:02

364

Views

Is deadlock possible in this simple scenario?

Published on 27 December 2016 at 07:33

score 348 · Answer 7 · 2017-01-02 12:58:05

348

Views

Are memory fences required here?

Published on 02 January 2017 at 12:58

score 449 · Answer 8 · 2017-01-01 21:39:39

449

Views

lock-free synchronization, fences and memory order (store operation with acquire semantics)

Published on 01 January 2017 at 21:39

score 178 · Answer 9 · 2014-11-10 21:38:26

178

Views

C Variable Not Updating on Thread Iteration

Published on 10 November 2014 at 21:38

score 795 · Answer 10 · 2014-11-13 21:37:58

795

Views

Do I need to use volatile keyword for memory access in critical section?

Published on 13 November 2014 at 21:37

score 234 · Answer 11 · 2013-11-27 11:52:16

234

Views

Does Sleep not have synchronization semantic?

Published on 27 November 2013 at 11:52

score 2.3k · Answer 12 · 2013-12-02 10:43:45

2.3k

Views

What is the impact SFENCE and LFENCE to caches of neighboring cores?

Published on 02 December 2013 at 10:43

score 22k · Answer 13 · 2013-12-01 19:19:06

22k

Views

Does it make any sense to use the LFENCE instruction on x86/x86_64 processors?

Published on 01 December 2013 at 19:19

score 327 · Answer 14 · 2013-12-07 21:36:51

327

Views

Determining the location for the usage of barriers (fences)

Published on 07 December 2013 at 21:36

score 1.2k · Answer 15 · 2013-12-12 17:14:44

1.2k

Views

Memory barriers and Linux kernel spinlock on TILE-Gx

Published on 12 December 2013 at 17:14

score 474 · Answer 16 · 2017-08-30 09:05:54

474

Views

Why don't we need volatile with StampedLock?

Published on 30 August 2017 at 09:05

score 490 · Answer 17 · 2017-08-30 22:19:14

490

Views

Is the example in the membarrier man page pointless in x86?

Published on 30 August 2017 at 22:19

score 774 · Answer 18 · 2017-09-15 07:10:44

774

Views

How to implement a atomic operation?

Published on 15 September 2017 at 07:10

score 3.4k · Answer 19 · 2011-02-11 17:26:58

3.4k

Views

sequentially-consistent atomic load on x86

Published on 11 February 2011 at 17:26

score 187 · Answer 20 · 2011-02-27 08:47:40

187

Views

Full memory barrier and ExclusiveReceiverGroup

Published on 27 February 2011 at 08:47

List Question

Why is the standard C# event invocation pattern thread-safe without a memory barrier or cache invalidation? What about similar code?

Does C++11 guarantee memory ordering between a release fence and a consume operation?

Memory barriers force cache coherency?

Spin locked stack and memory barriers (C++)

Lock-free stack: visibility issue when checking hazard pointers during pop()?

Is deadlock possible in this simple scenario?

Are memory fences required here?

lock-free synchronization, fences and memory order (store operation with acquire semantics)

C Variable Not Updating on Thread Iteration

Do I need to use volatile keyword for memory access in critical section?

Does Sleep not have synchronization semantic?

What is the impact SFENCE and LFENCE to caches of neighboring cores?

Does it make any sense to use the LFENCE instruction on x86/x86_64 processors?

Determining the location for the usage of barriers (fences)

Memory barriers and Linux kernel spinlock on TILE-Gx

Why don't we need volatile with StampedLock?

Is the example in the membarrier man page pointless in x86?

How to implement a atomic operation?

sequentially-consistent atomic load on x86

Full memory barrier and ExclusiveReceiverGroup

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