Question

ARM: Disabling MMU and updating PC

score 2.8k · Answer 1 · 2024-12-30 20:53:46

2.8k

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ARM: Disabling MMU and updating PC

Published on 30 December 2024 at 20:53

score 3.6k · Answer 2 · 2024-12-30 21:15:35

3.6k

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Does context switch between processes invalidate the MMU(memory control unit)?

Published on 30 December 2024 at 21:15

score 1.4k · Answer 3 · 2024-12-30 20:56:54

1.4k

Views

Using MMU to implement resizable arrays

Published on 30 December 2024 at 20:56

score 936 · Answer 4 · 2024-12-30 20:57:21

936

Views

What does DMA Channel virtualization mean?

Published on 30 December 2024 at 20:57

score 2.1k · Answer 5 · 2024-12-29 20:23:43

2.1k

Views

What is PDE cache?

Published on 29 December 2024 at 20:23

score 1.4k · Answer 6 · 2024-12-31 10:26:18

1.4k

Views

Why does access to an unmapped location not generate a hardware exception (Microblaze)

Published on 31 December 2024 at 10:26

score 1.4k · Answer 7 · 2024-12-30 21:09:43

1.4k

Views

In ARMv7, is the address used in TTBR0 and TTBR1 physical or virtual

Published on 30 December 2024 at 21:09

score 179 · Answer 8 · 2024-12-30 21:07:21

179

Views

how does kernel code access memory at the assembly level

Published on 30 December 2024 at 21:07

score 1.7k · Answer 9 · 2024-12-30 21:09:42

1.7k

Views

Linux /proc/pid/smaps proportional swap (like Pss but for swap)

Published on 30 December 2024 at 21:09

score 2.6k · Answer 10 · 2025-01-03 05:34:07

2.6k

Views

What is the downside of updating ARM TTBR(Translate Table Base Register)?

Published on 03 January 2025 at 05:34

score 1.1k · Answer 11 · 2025-01-06 01:02:20

1.1k

Views

Problems enabling MMU on ARM Cortex-A8. CPU is S5PV210

Published on 06 January 2025 at 01:02

score 1.8k · Answer 12 · 2024-12-30 21:01:18

1.8k

Views

How does MMU deal with Memory mapped registers?

Published on 30 December 2024 at 21:01

score 72 · Answer 13 · 2024-12-30 21:18:25

72

Views

What is (special in) the elf format for static-pie? And what preforms the fixups to the GOT?

Published on 30 December 2024 at 21:18

score 37 · Answer 14 · 2024-12-30 21:18:53

37

Views

Why does it take so long for cpu to write memory after it has obtained the physical address?

Published on 30 December 2024 at 21:18

score 640 · Answer 15 · 2024-12-30 21:09:41

640

Views

Linker : how to place a block of data at a specific address boundary

Published on 30 December 2024 at 21:09

score 370 · Answer 16 · 2024-12-30 21:00:07

370

Views

mmu in arm: how to map kernel code (bare metal)

Published on 30 December 2024 at 21:00

score 931 · Answer 17 · 2024-12-25 22:59:11

931

Views

aarch64 MMU translation table

Published on 25 December 2024 at 22:59

score 468 · Answer 18 · 2024-12-30 21:15:12

468

Views

Is 'pgd' Attribute Physical or Virtual Address in mm_struct in Linux Kernel?

Published on 30 December 2024 at 21:15

score 708 · Answer 19 · 2024-12-30 21:13:38

708

Views

DMA write fails when dma_alloc_coherent is replaced with dma_map_single

Published on 30 December 2024 at 21:13

score 419 · Answer 20 · 2024-12-30 20:57:20

419

Views

Does instruction fetch go through the MMU?

Published on 30 December 2024 at 20:57

List Question

ARM: Disabling MMU and updating PC

Does context switch between processes invalidate the MMU(memory control unit)?

Using MMU to implement resizable arrays

What does DMA Channel virtualization mean?

What is PDE cache?

Why does access to an unmapped location not generate a hardware exception (Microblaze)

In ARMv7, is the address used in TTBR0 and TTBR1 physical or virtual

how does kernel code access memory at the assembly level

Linux /proc/pid/smaps proportional swap (like Pss but for swap)

What is the downside of updating ARM TTBR(Translate Table Base Register)?

Problems enabling MMU on ARM Cortex-A8. CPU is S5PV210

How does MMU deal with Memory mapped registers?

What is (special in) the elf format for static-pie? And what preforms the fixups to the GOT?

Why does it take so long for cpu to write memory after it has obtained the physical address?

Linker : how to place a block of data at a specific address boundary

mmu in arm: how to map kernel code (bare metal)

aarch64 MMU translation table

Is 'pgd' Attribute Physical or Virtual Address in mm_struct in Linux Kernel?

DMA write fails when dma_alloc_coherent is replaced with dma_map_single

Does instruction fetch go through the MMU?

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