how do conditional branches and instructions which update conditional flags operate in an out of order arm architecture?

Question

I have the following sequence of instructions:

Address     instr  Operands
4357128L    cmp  {"x1", "#16"}
4357132L    bne  {"4356768"}
4357136L    add  {"w19", "w6","#16"}
4357140L    add  {"x0", "x0", "#16"}
4357144L    bhi  {"4387895"}

after cmp is executed, the nzcv as well as the conditional flags are updated (eq_ne, hi_ls, cs_cc etc..). So in an out of order architecture, how is this executed? Lets consider ARM Cortex A77 for example. It has multiple integer execution units. So cmp and add instructions could be issued in the same cycle. So are the conditional flags only updated after the inorder commit? or since conditional flags are required to be updated, are they all not issued in the same cycle? Also the conditional branches cannot be issued until the inorder commit for the instruction prior to it is completed right? So they will be blocked in the issue stage ie.. 4357132L bne can be only issued to its execution unit only after 4357128L cmp gets commited. And 4356772L bhi can only be issued to its execution unit only after 4357140L add gets commited. Is my understanding right? Any input would be appreciated. Regards, Tom