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20
Devhide
2025-01-06 00:30:52
1k
Views
How can the processor discern a far return from a near return?
Published on
06 January 2025 at 00:30
#pointers
#x86
#return
#memory-segmentation
#micro-architecture
2.1k
Views
L1 caches usually have split design, but L2, L3 caches have unified design, why?
Published on
06 January 2025 at 00:31
#caching
#cpu-architecture
#cpu-cache
#micro-architecture
3.4k
Views
Way prediction in modern cache
Published on
03 January 2025 at 22:36
#caching
#cpu-architecture
#processor
#cpu-cache
#micro-architecture
274
Views
Why did Intel remove the 16-byte branch target alignment Coding Rule from the Optimization Reference Manual?
Published on
06 January 2025 at 00:32
#x86
#x86-64
#intel
#micro-optimization
#micro-architecture
558
Views
The execution process of the instruction and the realization in gem5?
Published on
06 January 2025 at 00:30
#x86
#cpu-architecture
#instructions
#gem5
#micro-architecture
1.1k
Views
How to look up what form of an instruction is used, by opcode or disassembly?
Published on
06 January 2025 at 00:31
#assembly
#x86-64
#disassembly
#machine-code
#micro-architecture
337
Views
vtune memory-access report showing incorrect output
Published on
06 January 2025 at 00:18
#performance
#intel
#intel-vtune
#micro-architecture
474
Views
Why does a loop transitioning from having its uops fed by the Uop Cache to LSD cause a spike in branch-misses?
Published on
06 January 2025 at 00:32
#x86-64
#cpu-architecture
#micro-optimization
#branch-prediction
#micro-architecture
144
Views
What's the microarchitecture used in the MIPS I.S.A?
Published on
06 January 2025 at 00:18
#mips
#cpu-architecture
#instruction-set
#micro-architecture
32.4k
Views
What are my available march/mtune options?
Published on
03 January 2025 at 23:03
#gcc
#command-line
#x86
#compiler-flags
#micro-architecture
180
Views
shifting registers to right in the mic-1 without fetches
Published on
06 January 2025 at 00:26
#cpu-architecture
#micro-architecture
#mic-1
97
Views
Where does the L1 data cache missing come from in blocked matrix mul on arm?
Published on
06 January 2025 at 00:31
#c
#caching
#arm
#matrix-multiplication
#micro-architecture
107
Views
Can you simulate a ransomware on gem5?
Published on
03 January 2025 at 22:45
#architecture
#sandbox
#malware
#gem5
#micro-architecture
92
Views
Based Indexed Addressing Mode Memory Sum
Published on
03 January 2025 at 22:54
#assembly
#cpu-architecture
#x86-16
#microprocessors
#micro-architecture
96
Views
Is machine code and assembly code part of the architecture?
Published on
06 January 2025 at 00:28
#assembly
#cpu-architecture
#machine-code
#instruction-set
#micro-architecture
115
Views
Is port blocked when data is fetching from cache or memory in CPU microarchitecture?
Published on
06 January 2025 at 00:32
#x86
#cpu
#cpu-architecture
#processor
#micro-architecture
423
Views
uops for integer DIV instruction
Published on
03 January 2025 at 23:03
#assembly
#x86
#x86-64
#cpu-architecture
#micro-architecture
223
Views
how do conditional branches and instructions which update conditional flags operate in an out of order arm architecture?
Published on
06 January 2025 at 00:32
#arm
#instruction-set
#instructions
#micro-architecture
840
Views
How does Load Store Queue work in the presence of MSHR?
Published on
06 January 2025 at 00:24
#queue
#cpu-architecture
#cpu-cache
#micro-architecture
3.6k
Views
What are the "long" and "short" scoreboards w.r.t. MIO/L1TEX?
Published on
06 January 2025 at 00:24
#cuda
#gpu
#gpgpu
#micro-architecture
#nsight-compute
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