how to add two 16-bit STD_LOGIC_VECTOR and a carry into 17-bit in VHDL?

Question

i have two input 16-bit LOGIC_VECTOR A,B and a Cin:

A,B : in STD_LOGIC_VECTOR(15 DOWNTO 0);
Cin : in STD_LOGIC;
F : out STD_LOGIC_VECTOR(15 downto 0);
Cout : out STD_LOGIC 

and 17-bit LOGIC_VECTOR result signal :

signal result : STD_LOGIC_VECTOR(16 DOWNTO 0);

and the following code to add A and B and Cin :

result <= ('0' & A) + ('0' & B) + Cin;
F <= result(15 DOWNTO 0);
Cout <= result(16);

but it just add A,B and Cin is ignored. how can i make this right?

testbench:

A <= "1010100101110011";
B <= "0001111101010101";
Cin <= '1';

but the F is :

1100100011001000

Answer 1

Verify your connections, your code works as written. I tried the following:

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity adder is
    port (
        A, B : in  std_logic_vector(15 downto 0);
        Cin  : in  std_logic;
        F    : out std_logic_vector(15 downto 0);
        Cout : out std_logic
    );
end entity adder;

architecture rtl of adder is
    signal result : std_logic_vector(16 downto 0);
begin
    result <= ('0' & A) + ('0' & B) + Cin;
    F      <= result(15 downto 0);
    Cout   <= result(16);
end architecture rtl;

library ieee;
use ieee.std_logic_1164.all;

entity adder_tb is
end entity adder_tb;

architecture behavioral of adder_tb is
    signal A, B, F : std_logic_vector(15 downto 0);
    signal Cin, Cout : std_logic;
begin

    DUT: entity work.adder
    port map (
        A    => A,
        B    => B,
        Cin  => Cin,
        F    => F,
        Cout => Cout
    );

    A   <= "1010100101110011";
    B   <= "0001111101010101";
    Cin <= '1';

end architecture behavioral;

And got:

Where F = 1100100011001001, as expected.