How to get .bench file from verilog file

Question

Test.v is here:

module test(input A, B, C, D, E, output Y);
    assign Y = ((A^B)&C)^(D&E);
endmodule

Firstly I get .blif file by yosys (I use mycells.lib because I want only simple gates in bench file):

read_verilog test.v
hierarchy -check -top test
proc; opt; memory; opt;
techmap; opt
dfflibmap -liberty ../yosys/manual/PRESENTATION_Intro/mycells.lib 
abc -liberty ../yosys/manual/PRESENTATION_Intro/mycells.lib
write_blif test.blif

I get the following test.blif file:

# Generated by Yosys 0.9+3746 (git sha1 ec410c9b, gcc 9.3.0-17ubuntu1~20.04 -fPIC -Os)

.model test
.inputs A B C D E
.outputs Y
.names $false
.names $true
1
.names $undef
.subckt NAND A=D B=E Y=$abc$80$new_n7_
.subckt NOR A=A B=B Y=$abc$80$new_n8_
.subckt NAND A=A B=B Y=$abc$80$new_n9_
.subckt NAND A=C B=$abc$80$new_n9_ Y=$abc$80$new_n10_
.subckt NOR A=$abc$80$new_n8_ B=$abc$80$new_n10_ Y=$abc$80$new_n11_
.subckt NAND A=$abc$80$new_n7_ B=$abc$80$new_n11_ Y=$abc$80$new_n12_
.subckt NOR A=$abc$80$new_n7_ B=$abc$80$new_n11_ Y=$abc$80$new_n13_
.subckt NOT A=$abc$80$new_n13_ Y=$abc$80$new_n14_
.subckt NAND A=$abc$80$new_n12_ B=$abc$80$new_n14_ Y=Y
.end

I exit "yosys" and enter "yosys-abc" to generate .bench file. But I got the model error below:

abc 01> read_blif test.blif 
Line 10: Cannot find the model for subcircuit NAND.
Reading network from file has failed.
abc 01> 

How can I get test.bench file? Thanks..

Answer 1

It's related to your library (mycells.lib) and generating blif file. Your blif file should have ".gate" instead of ".subckt". You can use this command:

write_blif -gates test.blif