Question

Computed verilog parameter in Yosys

score 935 · Answer 1 · 2017-01-03 12:28:25

935

Views

Computed verilog parameter in Yosys

Published on 03 January 2017 at 12:28

score 4.4k · Answer 2 · 2017-01-06 05:30:00

4.4k

Views

How can I use iCE40 4K block RAM in 512x8 read mode with IceStorm?

Published on 06 January 2017 at 05:30

score 358 · Answer 3 · 2017-09-13 12:40:13

358

Views

Yosys instruction "sat -dump_cnf "

Published on 13 September 2017 at 12:40

score 189 · Answer 4 · 2020-10-04 05:26:27

189

Views

In Yosys I am getting a Warning saying Literal has a width of 8 bit, can anyone elaborate on it

Published on 04 October 2020 at 05:26

score 820 · Answer 5 · 2020-10-09 17:10:08

820

Views

How to pass Induction in SymbiYosys?

Published on 09 October 2020 at 17:10

score 148 · Answer 6 · 2023-11-02 04:19:44

148

Views

yosys: Generate Graphviz representation of design without running 'hierarchy'

Published on 02 November 2023 at 04:19

score 47 · Answer 7 · 2023-11-10 09:19:47

47

Views

Can I use yosys in Visual Studio Code with connect to WSL

Published on 10 November 2023 at 09:19

score 311 · Answer 8 · 2023-12-02 19:41:59

311

Views

Verilog/SystemVerilog: "constant" function is considered non-constant

Published on 02 December 2023 at 19:41

score 93 · Answer 9 · 2023-12-07 21:11:23

93

Views

In FPGA, why counter with full adder raw implementation have better clock performance than infered addition '+'?

Published on 07 December 2023 at 21:11

score 465 · Answer 10 · 2020-11-28 16:31:06

465

Views

ABC synthesis - read_liberty

Published on 28 November 2020 at 16:31

score 388 · Answer 11 · 2020-11-29 15:06:02

388

Views

Strange behaviour of yosys on FSM while building for iCE40

Published on 29 November 2020 at 15:06

score 338 · Answer 12 · 2020-12-04 09:20:48

338

Views

Is there an option to synthsise some code into verilog built-in primitives?

Published on 04 December 2020 at 09:20

score 649 · Answer 13 · 2020-12-03 16:31:04

649

Views

ghdl-yosys-plugin compilation failed

Published on 03 December 2020 at 16:31

score 90 · Answer 14 · 2020-12-11 17:58:54

90

Views

Executing additional command in Backend that takes the to be generated file

Published on 11 December 2020 at 17:58

score 113 · Answer 15 · 2022-05-02 03:14:59

113

Views

why are SB_LUT4 and SB_DFF not being packed by nextpnr?

Published on 02 May 2022 at 03:14

score 93 · Answer 16 · 2022-05-03 10:21:01

93

Views

Does operator of `[]` of std::map always put the new item into the first place of iterator?

Published on 03 May 2022 at 10:21

score 711 · Answer 17 · 2021-05-05 08:02:42

711

Views

How to get .bench file from verilog file

Published on 05 May 2021 at 08:02

score 282 · Answer 18 · 2020-09-03 12:58:19

282

Views

Addition/Substraction Optimization in Yosys

Published on 03 September 2020 at 12:58

score 218 · Answer 19 · 2020-09-10 07:37:25

218

Views

Is it possible to use $display to print some values when proving with yosys-smtbmc?

Published on 10 September 2020 at 07:37

score 1.6k · Answer 20 · 2020-09-21 17:41:03

1.6k

Views

Synthesis on yosys

Published on 21 September 2020 at 17:41

List Question

Computed verilog parameter in Yosys

How can I use iCE40 4K block RAM in 512x8 read mode with IceStorm?

Yosys instruction "sat -dump_cnf "

In Yosys I am getting a Warning saying Literal has a width of 8 bit, can anyone elaborate on it

How to pass Induction in SymbiYosys?

yosys: Generate Graphviz representation of design without running 'hierarchy'

Can I use yosys in Visual Studio Code with connect to WSL

Verilog/SystemVerilog: "constant" function is considered non-constant

In FPGA, why counter with full adder raw implementation have better clock performance than infered addition '+'?

ABC synthesis - read_liberty

Strange behaviour of yosys on FSM while building for iCE40

Is there an option to synthsise some code into verilog built-in primitives?

ghdl-yosys-plugin compilation failed

Executing additional command in Backend that takes the to be generated file

why are SB_LUT4 and SB_DFF not being packed by nextpnr?

Does operator of `[]` of std::map always put the new item into the first place of iterator?

How to get .bench file from verilog file

Addition/Substraction Optimization in Yosys

Is it possible to use $display to print some values when proving with yosys-smtbmc?

Synthesis on yosys

Trending Questions

Popular # Hahtags

Popular Questions