I'm using a SOC baremetal system based on CycloneV SX with ARM based CortexA9 Dual Core HPS inside.
To ensure the synchronization of the two cores in the dual-core system, I use a 50us timer interrupt.
When the FPGA generates a 50us timer pulse, my FPGA will generate two interrupt signals, Sig1 and Sig2. Sig1 is responsible for Core0, Sig2 is responsible for Core1.
Sig1 and Sig2 are sent to the HPS GIC at the same time. If these two signals are edge-triggered and have the same priority (they should be), the GIC seems to only respond to one of them.
My solution is to delay one signal for a period of time, or use level-triggering. Because the frequency is very high (50us), a little delay is very fatal.
If level-triggering is used,
Do I need to keep the interrupt signal set during the interrupt process, and reset it after the interrupt service program ends, or just need the level signal to hold for a period of time, and let the FPGA reset itself?
Do you have a better solution for that? Any idea is welcome.