I would like to do a sum of signals that I have in a list, naturally I have used variable and for (as I would in VHDL):
@always_comb
def sum():
sum = 0
for i in range(len(summands)):
sum = sum + summands[i]
product.next = sum
The problem is that this will use integer (in VHDL) for sum variable, which is not much useful when the width of sum will be more than 32bits.
So I tried to do something like this:
@always_comb
def sum():
sum = intbv(0, min=vmin, max=vmax)
for i in range(len(summands)):
sum = sum + summands[i]
product.next = sum
I get following error (during conversion):
Type mismatch with earlier assignment: sum
Which I don't understand how to work around. I guess it gets the value of intbv in sum as integer and therefore is different type.
Thanks for any suggestion
For people who come across this in future. You can create the variable outside the
@always_comb
(or@always
) function:The syntax to assign to that variable is:
The given example would then become:
This page in the MyHDL manual provides more detail.