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Is an inferred latch in Quartus II necessarily transparent

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#vhdl #fpga #synthesis #quartus
197
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VHDL, concurrent signal assignment wrong on FPGA but right in Modelsim

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#signals #vhdl #fpga #modelsim
3.7k
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Read file in FPGA

Published on
#vhdl #fpga #xilinx
56
Views

xilinx sdka error when using lwip library

Published on
#fpga #lwip #microblaze #xilinx-edk
315
Views

How to demonstrate a 32-bit MIPS with FPUs in a FPGA?

Published on
#mips #verilog #fpga #system-verilog #mips32
1.5k
Views

How to get rid of scale factor from CORDIC

Published on
#math #vhdl #fpga #register-transfer-level #cordic
2.7k
Views

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#verilog #fpga #spi #serial-communication
2.1k
Views

Using C programming to call VHDL implementation

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#c #vhdl #fpga #xilinx #xilinx-ise
590
Views

Why we use CORDIC gain?

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#math #fpga #cordic
2.8k
Views

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Published on
#fpga #uart #intel-fpga #quartus #qsys
311
Views

What is the cause of Vivados 'synth 8-1027' error?

Published on
#vhdl #fpga #xilinx #vivado
1.4k
Views

How to change timescale of VCD file dumped?

Published on
#c++ #fpga #chisel
550
Views

Sync two FPGAs to generate same Sine Wave

Published on
#verilog #fpga #lookup-tables #master-slave #trigonometry
92
Views

Connect stack of Parallela boards and a rPI via FPGA and 1/0 pins

Published on
#performance #raspberry-pi #fpga #low-latency #parallella
5.2k
Views

Error synthesizing hierarchical names in vivado

Published on
#verilog #fpga #system-verilog #xilinx #vivado
255
Views

a C program to test MIPS processor with my FPGA board

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#c #mips #cross-compiling #fpga
1.9k
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swap two variables in verilog using XOR

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#verilog #fpga #xor #hdl
2.6k
Views

How to use the Xilinx Division IP Core

Published on
#vhdl #fpga #xilinx #divider
611
Views

Fatal exception in interrupt zcu102 GPIO PL Interrupt Petalinux

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#linux-kernel #fpga #xilinx #gpio #interrupt-handling
2.3k
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#verilog #fpga #nios

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