How to pass a variable to the define macro used for accessing the path in system verilog

Question

I am using a define macro to set the path for a module, ie, `define DUT_PATH(CH) dut_top.u_channel_```CH``_mode

and using this define macro in a module where we are passing the channel number ,

module channel_oper # (int channel_num = 0) ( input logic addr_base; ) ;

assign addr_base = `DUT_PATH(channel_num).addr_base ;

endmodule

In the top file , we are calling the module as

channel_oper(3); //channel_oper(channel_num)

where I expect the output of the addr_base to be dut_top.u_channel_3_mode.addr_base , but I am getting the value assigned as dut_top.u_channel_channel_num_mode.addr_base and cross dereferenece error .

Can you please provide me a solution or any suggestions for this to use a parameterised vaiable to the define macro.

In this case, genvar or generate block could not be used as this is not used for any manipulation . This is used to access the different path for the different channel number and we are passing the channel number from the top module . The module channel operation takes the channel number from the parameter and goes to that particular channel path and takes the vaiable.

Answer 1

Here is an example which could work in some cases (works in synopsys vcs/system verilog). It generates an instance name per channel but in a bit different form. It automatically inserts [num] from the loop iteration and also inserts an additional hierarchy for the 'if' statement, i named it as 'number'. You also would need to know the max number of channels to organize your loop correctly.

module top;
   mod#(1) mod1();
   mod#(4) mod2();
endmodule // top

module mod#(int P = 0);
   for (genvar i = 0; i < 10; i++) begin: channel
      if (i == P) begin:number
        mx mx();
      end
   end
endmodule

module mx;
   initial
     $display("%m");
   initial #2 $finish;
endmodule // mx

Now, here are the lists of the 'mx' instances:

top.mod1.channel[1].number.mx
top.mod2.channel[4].number.mx