How to synchronise a bundle between 2 clock domains in chisel

129 Views Asked by At

I'm trying synchronise a bundle of signals between 2 modules in different clock domain. I can do it by manually instantiating AsyncQueue between them , and also take care of hooking the clock & reset for each side. It seems like there is a seem-less way to do that with AsyncBundle and I need some guidelines on understanding how to do it. in source side (at clkA) I have :

val ioA = IO(Decoupled(UInt(32.W))

On the sink side (at clkB) I have:

val ioB = IO(Decoupled(UInt(32.W).flip)

So it make sense (I'm not sure the below code s correct) to do some thing like this:

// in module A
val ioA = IO(new AsyncBundle(Decoupled(UInt(32.W))))

// in module B
val ioB = IO (new AsyncBundle(Decoupled(UInt(32.W)).flip) 

// and somewhere in a module that contains both modules
b.io <> FromAsyncBundle(a.io)

does the above make sense? also I've noticed that FromAsyncBundle creates a DecoupledIO does it replace the one i defined in the bundle or is it just for crossing? if it does replace how do I drive it, for example push data & valid from some logic. What about the clock which clock each side of the crossing will get ?

0

There are 0 best solutions below