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20
59
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Adding a trivial bridge in FireSim

Published on
#scala #uart #chisel #bridge #rocket-chip
41
Views

Confusion regarding stage2 and stage2final in PTW.scala

Published on
#rocket-chip
123
Views

Build rocket-tools for gcc-13

Published on
#rocket-chip
155
Views

Install rocket-chip on Ubuntu

Published on
#rocket-chip
249
Views

multiple definition of `bitbang_swd' when building rocket-chip tools

Published on
#rocket-chip
430
Views

Implementing a diplomatic AXI Stream interface in Chisel - BundleMap.cloneType error

Published on
#chisel #rocket-chip
307
Views

Adding a MMIO peripheral to a small rocket core

Published on
#rocket-chip
570
Views

Differences between LazyModule and LazyModuleImp

Published on
#riscv #chisel #rocket-chip #firrtl
64
Views

Increasing AsIDBits from zero

Published on
#riscv #chisel #rocket-chip
479
Views

option method of boolean Scala / Chisel

Published on
#scala #chisel #rocket-chip
1k
Views

Unrecognized opcode in creating custom RISC-V instruction

Published on
#riscv #rocket-chip #riscv32
448
Views

How to synthesis Rocket-Chip on Vivado?

Published on
#vivado #synthesis #chisel #rocket-chip
298
Views

How to config xLen in rocket core?

Published on
#riscv #chisel #rocket-chip
619
Views

What is the meaning of :*= and :=* operators?

Published on
#chisel #rocket-chip
506
Views

What do the (site, here, up) arguments mean when creating rocket-chip configurations?

Published on
#chisel #rocket-chip
229
Views

How do I run a single UnitTest from rocket-chip?

Published on
#chisel #rocket-chip
167
Views

what is "wxd" in rocketcore?

Published on
#riscv #chisel #rocket-chip
1.4k
Views

Any way to work around JVM code size limits tripped by large Chisel file

Published on
#scala #jvm #chisel #rocket-chip
124
Views

How to synchronise a bundle between 2 clock domains in chisel

Published on
#chisel #rocket-chip
278
Views

IP block generation/testing when using diplomacy. Possible to give dummy node?

Published on
#chisel #rocket-chip

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