I don't understand how to do this Lesson :'(

Question

Lesson 2: Design an address decoder for 64 KB memory from 16KB memory ICs, knowing that the memory base address is 94000H and the address decoder is designed using circuits combinatorial logic.

Answer 1

64KB is four times 16KB, so you will need four 16KB memory chips. Addressing 64 KB = 2¹⁶ bytes of memory requires 16 wires between CPU and the memory chips. Let's enumerate those wires as 0..15:

       15   11    7    3  0 
        |    |    |    |  | 
lowest: 0000_0000_0000_0000b
highest:1111_1111_1111_1111b

Your 16KB chips use only addressing pins 0..13, connect them all in parallel to the address bus. The remaining pins 14..15 need to be decoded to four chip-select (CS) signals, connected each to their corresponding 16KB chip and causing the chip idle when CS is not 1.

Combinatorial logic of the decoder is straightforward:

CPU pins   CS3 CS2 CS1 CS0
15 14
 0  0       0   0   0   1
 0  1       0   0   1   0
 1  0       0   1   0   0
 1  1       1   0   0   0  

Construction of the decoder depends on available logical gates, for instance CS0 should be 1 if and only if both pins 14 and 15 area 0, so you may need two input invertors and one AND gate.

Remapping the address space to 94000H

       19   15   11    7    3  0 
        |    |    |    |    |  | 
94000h: 1001_0100_0000_0000_0000b

affects only address bit 14 of 64KB memory, so you should invert this bit on input of your four CS decoders and you can ignore addressing pins 16..19.