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20
Devhide
2025-01-05 02:31:10
295
Views
Assembly language, don't understand the instruction codes and memory locations
Published on
05 January 2025 at 02:31
#assembly
#digital-logic
#68hc12
126
Views
What is the component for if-clause in digital logic?
Published on
05 January 2025 at 02:28
#vhdl
#digital-logic
2.6k
Views
Time complexity in n bit array multiplication
Published on
05 January 2025 at 02:27
#complexity-theory
#digital-logic
2.4k
Views
Design does not fit ispLEVER
Published on
01 January 2025 at 17:02
#vhdl
#digital-logic
#digital-design
2.5k
Views
A program that would test two input gates (AND, OR, NAND, NOR, and XOR)
Published on
05 January 2025 at 02:29
#boolean
#arduino
#logic
#ttl
#digital-logic
580
Views
Is it possible to avoid specifying a default in order to get an X in Chisel?
Published on
05 January 2025 at 02:31
#hardware
#hdl
#synthesis
#digital-logic
#chisel
3.1k
Views
Verilog: Store counter value when reset is asserted
Published on
05 January 2025 at 02:28
#verilog
#digital-logic
507
Views
Chisel runtime error in test harness
Published on
05 January 2025 at 02:26
#scala
#hardware
#synthesis
#digital-logic
#chisel
12.8k
Views
Why K-map has states in sequence of 00,01,11,10 instead of 00,01,10,11?
Published on
05 January 2025 at 02:29
#digital
#digital-logic
442
Views
Does modeling digital circuits in C have any practical benefits as opposed using the language's standard operations?
Published on
05 January 2025 at 02:32
#c
#gcc
#hardware
#digital-logic
495
Views
Digital Logic Fundamentals Binary Division Hardware Designing
Published on
05 January 2025 at 02:29
#binary
#hardware
#division
#digital-logic
96
Views
Non Restoring Division in Iverilog
Published on
05 January 2025 at 02:25
#digital-logic
#iverilog
894
Views
Digital logic - mealy state machines?
Published on
05 January 2025 at 02:25
#hardware
#state-machine
#circuit
#digital-logic
844
Views
Digital Logic - Karnaugh Map
Published on
02 January 2025 at 23:22
#circuit
#digital-logic
#truthtable
#karnaugh-map
85
Views
How to simplify circuits
Published on
05 January 2025 at 02:24
#logic
#computer-science
#cpu-architecture
#circuit
#digital-logic
85
Views
Multiplication table in VMLab / AVR
Published on
05 January 2025 at 02:25
#avr
#digital-logic
744
Views
If the PC register is simultaneously read and written, does its read data contain the previous data or the newly-written data?
Published on
05 January 2025 at 02:32
#cpu-architecture
#digital-logic
#flip-flop
5.6k
Views
conversion from binary to base 10 using floating point conversion
Published on
05 January 2025 at 02:29
#floating-point
#binary
#computer-science
#digital-logic
1.2k
Views
Implementation of 8:1 MUX using 3:8 decoders and 2 input gates
Published on
05 January 2025 at 02:29
#cpu-architecture
#decoder
#digital-logic
81
Views
I don't understand how to do this Lesson :'(
Published on
05 January 2025 at 02:25
#cpu-architecture
#circuit
#digital-logic
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