I want to order two signals to one input in vhdl

Question

I want to have two signals (overflow1 and set1) for one input(tick).

counter2 : counter
generic map (border => 5, width => 4)
port map (RST => RST,
       tick => overflow1 [...] set1, -- overflow1 and set1 are these signals  
   enable => SW0,
       x => count2,
   overflow => overflow2);  

so i want to fill the gap there. i hope u can understand my Problem. thanks

Answer 1

Assuming that tick is an input port, and overflow1 and set1 are std_logic, then in VHDL-2008 you can do overflow1 or set1.

In previous VHDL versions, like VHDL-2002 and before, you must make an internal temporary signal like temp <= overflow1 or set1, and use that to drive the port.