In Intels extended page table (EPT), does the TLB cache guest virtual address to guest physical address?

Question

I am reading about Intel's EPT to support virtualization. I read about the nested page table. My question is, does the TLB caches guest VA to guest PA as well as guest PA to host machine address? or is it just virtual address to machine address?

Answer 1

If there is only "conventional" TLB then it stores HVA to HPA (machine addess) but now some processors are available with other Virtualization specific TLBs which store intermediary translation.

Answer 2

No. I do not think this is useful for TLB to keep mappings from guest linear address to guest physical address. My understanding is that the TLB entry should only contain mappings that can be used to generate a real physical address. According to Intel SDM, there might be three different type mappings in TLBs:

• linear to physical mapping
• guest physical to host physical mapping
• combined mapping

All these three mappings generate host page frame numbers, not the guest ones.

Note: I used the term "linear address" instead of "virtual address", because it's a more accurate term to use if we consider the segmentation process.