I'm kinda new here so I'm trying to figure out the basics first, so I'm looking into MARIE assembly, I noticed that MAR sometimes is just the value of PC but minus 1, is there a reason behind this or is it just a coincidence?
Looking into it now, I also noticed that IR and MBR has the same values sometimes; why is that so?
It is not coincidence. What you're seeing is due to combination of (a) different instruction types and (b) where the simulator is pausing to show the values of these registers, probably in between instructions.
The MAR — Memory Address Register — is the only way that this processor communicates with memory regarding where to read/load or write/store.
The MBR — Memory Buffer Register — is used to hold the data being read or written during memory transfer operations.
The MAR is used both for instruction fetch and any data load or data store operation.
The instruction fetch sequence involves
The processor fetches the instruction by copying the PC value into the MAR and asserting a read signal — the memory responds by reading that memory location and placing its contents into the MBR. The processor then copies the instruction in the MBR into the IR for instruction decode.
During instruction execution, the PC is advanced, usually to point to the next instruction.
If an instruction does not perform a data load or data store operation — as is the case with SkipCond, Input, Output, for example — then upon instruction completion you will see that the MAR is left holding the PC of the instruction, and the PC has been advanced, often by 1. Further, the IR and MBR will hold the same value — which is the machine code instruction. The MAR and MBR reflect the instruction fetch.
However, if the instruction does perform a data load or data store operation then upon instruction completion you will see the MAR holds the address of the data memory, and the MBR holds the data value transferred. These instructions still perform instruction fetch — and if you observe the registers at the right point in time during the execution of these instructions you'll see IR=MBR and MAR=PC, but as part of completion of these instructions, the MAR & MBR are reused for the data memory access.
All instructions are fetched from memory, but some instructions additionally do data loads / stores.
Bottom line is that the MAR & MBR hold values used in the most recent memory operation (whether instruction fetch or data load/store) even after that memory operation has completed (until they are reused for the next instruction fetch).
On some other processors, there is a separate instruction memory and separate data memory, so there are effectively two MAR's and two MBR's, and the PC is the MAR for the instruction memory. These may be caches that are then unified to shared main memory.
(Separate memories is called a Harvard architecture; a simple one like MARIE with no instruction prefetch buffer or instruction cache could use the PC directly as the MAR. If PC updates to the next instruction after fetching, it can be fetching the next instruction while executing the current one using PC as an MAR.)