near "when": syntax error in VHDL

Question

I'm trying to write some code to simulate a circuit with two tri-state buffers and a pull-up resistor in VHDL. Below is my code:

library ieee;
use ieee.std_logic_1164.all;

entity PullUpResistor is
port (
A, S, B, T : IN std_logic;  -- select one of these four inputs
TriOut : OUT std_logic -- output (no ";" after last port)
);
end entity PullUpResistor;

architecture behavioral of PullUpResistor is
begin
process(A, S, B, T) is
when (S = '1') and (T = '0') => TriOut <= A;
when (S = '0') and (T = '1') => TriOut <= B;
when (S = '0') and (T = '0') => TriOut <= 'H';
when (S = '1') and (T = '1') => TriOut <= 'X';
end process;
end architecture behavioral;

I'm getting a compiler error near "when": syntax error on line 14 which is the when (S = '1') and (T = '0') => TriOut <= A; line. I can't for the life of me figure out what the syntax error is.

Any help would be greatly appreciated.

Thanks.

Answer 1

Two things. There is no is needed after process. And more importantly, when can't be used like that. You can do what you want to concurrently:

TriOut <=
  A when S = '1' and T = '0' else
  B when S = '0' and T = '1' else
  ...

or in a process:

process (A, S, B, T)
begin
  if S = '1' and T = '0' then
    TriOut <= A;
  elsif ...

(or with VHDL-2008, a combination of the two.)

You appear to be using when as if it's in a case statement. With that in mind, you could also do (in a process):

sel <= S & T;

case sel is
  when "10" =>
    TriOut <= A;
  when "01" =>
    TriOut <= B;
  ...

What you can't do is mix and match.