Why is the wired or signal type (wor) disallowed for typedefs in SystemVerilog

Question

In SystemVerilog I CAN do

typedef logic [15:0] bus16;
typedef reg [15:0] reg16;

interface myif;
   bus16 mybus;
   wor [15:0] myotherbus;
endinterface

But I CAN'T do

typedef wor [15:0] wor16;

interface myif;
   wor16 myotherbus;
endinterface

I get "unknown variable declaration type"

It seems, at least in my Synplicity version, typedefs of 'wor' is not permitted.

Is this a limitation defined in the IEEE1800 spec or is it perhaps a bug?

Answer 1

It is disallowed because System Verilog Standard does not allow using nets in typedefs. Sorry, no other explanation.

You can look at the syntax in paragraph 6.18. Follow data_type definition. It is based on system verilog vars but does not include nets (6.8).

You can define a new net type using the nettype construct, but it still does no allow you to use other net types. However, you can create them with a custom resolution behavior (check 6.6.7). It is a special syntax and does not fit for simple renaming. BTW, neither wor nor this are synthesizable.

So, your best bet is to use macros: `define wor16 wor[15:0]

Answer 2

SystemVerilog separates the concepts of network/net types (which are like resolved signals in VHDL) and variables (unresolved) from data types. The net types wire, wand, wor, etc. have built-in resolution functions with a default data type of logic. The following net declarations are equivalent:

wor [15:0] w;
wor logic [15:0] w;
typedef logic [15:0] bus16;
wor bus16 w;

Similarly the following variable declarations are equivalent:

logic [15:0] v;
var logic [15:0] v;
typedef logic [15:0] bus16;
var bus16 v;
bus16 v;

In most places, the var keyword is implicit when declaring variables.

There is a nettype declaration that binds a data type with a user-defined resolution function. Unfortunately there no way to define a nettype with one of the built-in resolution functions, so you would have to write your own or function.