Is it possible to have two instance have same name in the netlist?

Question

Is it possible to have two flops/any other instances have the same name in the netlist?

Considering that there is no hierarchy, say I have a design of 10M instances and there exists an flop called foo, is it possible that another flop have same name 'foo'?

Answer 1

The only way your question makes sense is to consider one large verilog file - obviously, here there can't be more than one reg/logic with the name foo. This is fundamental to the verilog scoping rules.

If there is any iteration or local scope of any form in your design, the elaboration process will construct a form of heirarchy to handle this iteration. If you flatten the resulting netlist (by default or design), then each element will either gain an abstract unique identifier (n1, n2, n3...), or be pre/post fixed with some heirarchical information (gen_1_foo, gen_2_foo...).

After the netlist generation, it may be non-trivial to relate a specific flop to it's syntactic source in the verilog - but you brought this on yourself by the lack of heirarchy and structure in the design.

Answer 2

No. Within a single scope, you cannot re-use the same identifier for another purpose,

Answer 3

As Dave says, no. But if you had 10M instances, you wouldn't have coded that manually, your logic synthesiser would have. And it won't output an illegal netlist.