Is there an option to synthsise some code into verilog built-in primitives?

Question

I thought that techmap without any argument will do it but it didn't. probably I missunderstand what 'logical synthsis' means.

basic example:

AND_GATE.v:

module AND_GATE( input A, input B, output X);
    assign X = A & B;
endmodule

yosys> read_verilog AND_GATE.v
yosys> synth
....................
   Number of wires:                  3
   Number of wire bits:              3
   Number of public wires:           3
   Number of public wire bits:       3
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:                  1
     $_AND_                          1
yosys> abc -g AND,NAND,OR,NOR,XOR,XNOR
........................
3.1.2. Re-integrating ABC results.
ABC RESULTS:               AND cells:        1
ABC RESULTS:        internal signals:        0
ABC RESULTS:           input signals:        2
ABC RESULTS:          output signals:        1
Removing temp directory.

yosys> clean
Removed 0 unused cells and 3 unused wires.
yosys> write_verilog net.v

net.v

module AND_GATE(A, B, X);
  (* src = "AND_GATE.v:1" *)
  input A;
  (* src = "AND_GATE.v:1" *)
  input B;
  (* src = "AND_GATE.v:1" *)
  output X;
  assign X = B & A;
endmodule

Answer 1

Using something like synth; abc -g AND,NAND,OR,NOR,XOR,XNOR will map to a basic set of gates equivalent to the Verilog primitives - techmap on its own won't get you far away either - but the Yosys verilog backend doesn't have an option to use built-in primitives, it always writes the gates as their expression.