L1 cache ports in ARM Cortex processors

Question

I did some reseach, but could not find much information.

I'd like to know how many L1 read and L1 write ports ARM embedded processors have and how wide the ports are. Specifically, I am interested in Cortex-A8, Cortex-A9, and Cortext-A15.

My blind guess is that a Cortex-A9 processor has one L1 read port and one L1 write port which are 64 bits wide. My other guess is that it has a single shared read/write port. Any thoughts on that?

Answer 1

Afaik you should check the AXI capabilities of each processors.

For example page for Cortex-A9 contains a detailed table for AXI master interface attributes and states:

The Cortex-A9 MPCore L2 interface can have two 64-bit wide AXI bus masters.

Page for Cortex-A15 contains less information, stating:

The processor implements an AMBA 4 AXI Coherency Extensions (ACE) master interface and an AMBA 3 AXI Accelerator Coherency Port (ACP) slave interface. Both the ACE and ACP support a hardware configurable 64-bit or 128-bit data width.

There also exists a similar page or Cortex-A8.

Answer 2

These processors have separate L1 instruction and data caches. I'm pretty sure all ARM cores' L1 I-cache and D-cache each have 1 read and 1 write port Furber p.81.

L1 Cache is in each core, so for details I'd go to core TRM e.g. Cortex-A9 TRM rather than an MPCore TRM. Ch 7 there tells of 64-bit datapath for each.