In practice, when there's so many possible combinations using gates to arrive to a solution, what's some advice when analyzing bit behavior?
For instance, what's the general thought process to be able to anticipate how bits are going to flip in our favor using my non-code example:
If I have 2 Nand gate outputs tested 6 times:
110111 (let's call this first set)
101111 (let's call this second set)
You see the 0 instances above? Had they been aligned in the same output instance, I would have finished my gate logic. However, they're misaligned by one output instance. I felt I was close, but wasn't sure what to do.
I had to gate "shuffle" the bits of the first set like a deck of cards then compare it back to the original first set and eventually fulfilled the condition I needed for my gates to work. It felt like luck. I'm sure there's a better way to think about this.
It is very difficult to give you advice because your example is not specific and it is hard to understand exactly what your concern is. StackOverflow works best when you post a specific problem with actual code (HDL in this case).
With regards to optimization, it all depends on what you want to optimize for -- for example: code readability/simplicity / minimum number of gates / minimum gate delays (not an issue in NAND2Tetris but often is in real life).
As a general philosophy, I tend towards readability and simplicity first -- get something working that is understandable. Once you've got the assignment done, if you have extra time you can flex and try for minimizing the number of gates.
There are, btw, design tools that will take an arbitrary truth table and generate a minimal-gate solution.