I am a student and i have an exercise on MIPS and i need some guidance! Below is the exercise:
Consider the Data Processing Unit of MIPS architecture wired logic for a command cycle for single and multiple machine cycles. Describe the full flow of information and in both implementation cases - single and multiple machine cycles - for the command: bne $ 12, $ 4, -100 where -100 is the displacement of relative addressing commands. In particular, report all the values of the control signals produced, as well as the micro-processes performed in each DPU, in the order in which they are executed, whether useful for the mandate or not - which is requested to report. Also, write the information values that arrive at each subunit and each multiplexer. Finally, in the case of multiple machine cycles, please report the registers of the A, B, C, IR and DR registers occurring, as well as the values are recorded. Consider that the $ 12 and $ 4 registers contain the values at the beginning of the instruction cycle 8 and 0 respectively, while the PC contains the address 0x1480a008. How would the execution of the above command evolve if the $ 4 registrar is in the beginning of the command cycle contained the value of 8;
Thanks...