modelsim says: near ")": (vcom-1576) expecting IDENTIFIER. but fixing it gives more errors

Question

when using this code:

library IEEE;
use IEEE.Std_logic_1164.all;
use IEEE.Numeric_STD.all;

entity CLOCKDIVIDER_TB is
end entity CLOCKDIVIDER_TB;

architecture BENCH of CLOCKDIVIDER_TB is

--declare component
component ClockDivider
    Port(
        CLK            : IN STD_LOGIC;   
        RST            : IN STD_LOGIC;
        CLK_OUT_DIV_01 : OUT STD_LOGIC;
        CLK_OUT_DIV_02 : OUT STD_LOGIC;
        CLK_OUT_DIV_03 : OUT STD_LOGIC;
        CLK_OUT_DIV_04 : OUT STD_LOGIC;
    );
end component;

--inputs
signal CLK            : IN STD_LOGIC := '0';   
signal RST            : IN STD_LOGIC := '0';

--outputs   
signal CLK_OUT_DIV_01 : OUT STD_LOGIC;
signal CLK_OUT_DIV_02 : OUT STD_LOGIC;
signal CLK_OUT_DIV_03 : OUT STD_LOGIC;
signal CLK_OUT_DIV_04 : OUT STD_LOGIC;

--clock period
constant clk_t : time := 20 ns;

BEGIN

--uut instance
uut: ClockDivider PORT MAP (
    CLK  => CLK,
    RST  => RST,
    CLK_OUT_DIV_01 => CLK_OUT_DIV_01,
    CLK_OUT_DIV_02 => CLK_OUT_DIV_02,
    CLK_OUT_DIV_03 => CLK_OUT_DIV_03,
    CLK_OUT_DIV_04 => CLK_OUT_DIV_04
);

  -- Clock definition.
clk_process: process
begin
    CLK <= '0';
    wait for clk_t / 2;
    CLK <= '1';
    wait for clk_t / 2;
end process;

-- Processing.
stim_proc: process
begin
    wait for 100 ns;
    reset <= '1'; -- Up
    wait for 100 ns;
    reset <= '0'; -- Down
        wait;
end process;


end architecture BENCH;

I am getting the error:

** Error: D:\modelsim\week 2\ClockDivider_tb.vhd(27): near ")": (vcom-1576) expecting IDENTIFIER.

However, when fixing this error by removing the semicolon in the component declaration:

--declare component
component ClockDivider
    Port(
        CLK            : IN STD_LOGIC;   
        RST            : IN STD_LOGIC;
        CLK_OUT_DIV_01 : OUT STD_LOGIC;
        CLK_OUT_DIV_02 : OUT STD_LOGIC;
        CLK_OUT_DIV_03 : OUT STD_LOGIC;
        CLK_OUT_DIV_04 : OUT STD_LOGIC
    );

the program gives me the following errors:

** Error: D:\modelsim\week 2\ClockDivider_tb.vhd(31): near "IN": (vcom-1576) expecting STRING or IDENTIFIER or << or '('.
** Error: D:\modelsim\week 2\ClockDivider_tb.vhd(32): near "IN": (vcom-1576) expecting STRING or IDENTIFIER or << or '('.
** Error: D:\modelsim\week 2\ClockDivider_tb.vhd(35): near "OUT": (vcom-1576) expecting STRING or IDENTIFIER or << or '('.
** Error: D:\modelsim\week 2\ClockDivider_tb.vhd(36): near "OUT": (vcom-1576) expecting STRING or IDENTIFIER or << or '('.
** Error: D:\modelsim\week 2\ClockDivider_tb.vhd(37): near "OUT": (vcom-1576) expecting STRING or IDENTIFIER or << or '('.
** Error: D:\modelsim\week 2\ClockDivider_tb.vhd(38): near "OUT": (vcom-1576) expecting STRING or IDENTIFIER or << or '('.
** Error: D:\modelsim\week 2\ClockDivider_tb.vhd(47): (vcom-1136) Unknown identifier "CLK".
** Error: D:\modelsim\week 2\ClockDivider_tb.vhd(48): (vcom-1136) Unknown identifier "RST".
** Error: D:\modelsim\week 2\ClockDivider_tb.vhd(49): (vcom-1136) Unknown identifier "CLK_OUT_DIV_01".
** Error: D:\modelsim\week 2\ClockDivider_tb.vhd(50): (vcom-1136) Unknown identifier "CLK_OUT_DIV_02".
** Error: D:\modelsim\week 2\ClockDivider_tb.vhd(51): (vcom-1136) Unknown identifier "CLK_OUT_DIV_03".
** Error: D:\modelsim\week 2\ClockDivider_tb.vhd(52): (vcom-1136) Unknown identifier "CLK_OUT_DIV_04".
** Error: D:\modelsim\week 2\ClockDivider_tb.vhd(58): Illegal target for signal assignment.
** Error: D:\modelsim\week 2\ClockDivider_tb.vhd(58): (vcom-1136) Unknown identifier "CLK".
** Error: D:\modelsim\week 2\ClockDivider_tb.vhd(60): Illegal target for signal assignment.
** Error: D:\modelsim\week 2\ClockDivider_tb.vhd(60): (vcom-1136) Unknown identifier "CLK".
** Error: D:\modelsim\week 2\ClockDivider_tb.vhd(68): Illegal target for signal assignment.
** Error: D:\modelsim\week 2\ClockDivider_tb.vhd(68): (vcom-1136) Unknown identifier "reset".
** Error: D:\modelsim\week 2\ClockDivider_tb.vhd(70): Illegal target for signal assignment.
** Error: D:\modelsim\week 2\ClockDivider_tb.vhd(70): (vcom-1136) Unknown identifier "reset". 

I am not too sure why the program breaks when I fix syntax error.

I am also pretty new to the program and I'm not able to figure out what's wrong using other examples out there.

Does anyone know how to fix this?

Answer 1

Thanks for the help. I went over the code and managed to get it working. I realized my mistake that I confused reset and RST as well as removing the "IN" and "OUT" when declaring signals.

This is the working code:

library IEEE;
use IEEE.Std_logic_1164.all;
use IEEE.Numeric_STD.all;

entity CLOCKDIVIDER_TB is
end entity CLOCKDIVIDER_TB;

architecture BENCH of CLOCKDIVIDER_TB is

--declare component
component ClockDivider
    Port(
        CLK            : IN STD_LOGIC;   
        RST            : IN STD_LOGIC;
        CLK_OUT_DIV_01 : OUT STD_LOGIC;
        CLK_OUT_DIV_02 : OUT STD_LOGIC;
        CLK_OUT_DIV_03 : OUT STD_LOGIC;
        CLK_OUT_DIV_04 : OUT STD_LOGIC
    );
end component;

--signals
--inputs
signal CLK            : STD_LOGIC := '0';   
signal RST            : STD_LOGIC := '0';

--outputs   
signal CLK_OUT_DIV_01 : STD_LOGIC;
signal CLK_OUT_DIV_02 : STD_LOGIC;
signal CLK_OUT_DIV_03 : STD_LOGIC;
signal CLK_OUT_DIV_04 : STD_LOGIC;

--clock period
constant clk_t : time := 20 ns;

BEGIN

--uut instance
uut: ClockDivider PORT MAP (
        CLK  => CLK,
        RST  => RST,
        CLK_OUT_DIV_01 => CLK_OUT_DIV_01,
        CLK_OUT_DIV_02 => CLK_OUT_DIV_02,
        CLK_OUT_DIV_03 => CLK_OUT_DIV_03,
        CLK_OUT_DIV_04 => CLK_OUT_DIV_04
);



-- Clock definition.
clk_process: process
begin
        CLK <= '0';
        wait for clk_t / 2;
        CLK <= '1';
        wait for clk_t / 2;
end process;

-- Processing.
stim_proc: process
begin
    RST <= '1';
        wait for 1 ns;
        RST <= '0';
        wait for 2000000 ns;
        RST <= '1'; -- Up

    wait;
end process;


end architecture BENCH;