Multiple behaviours for single entity

Question

I wrote a VHDL Testbench which contains the following :

• Lots of signal declarations
• UUT instantiations / port maps
• A huge amount of one-line concurrent assignments
• Various small processes
• One main (big) process which actually stimulates the UUT.

Everything is fine except the fact that I want to have two distinct types of stimulation (let's say a simple stimulus and a more complex one) so what I did is I created two testbenches which have everything in common except the main big process. But I don't find it really convenient since I always need to update both when, for example, I make a change to the UUT port map. Not cool.

I don't really want to merge my two main process because it will look like hell and I can't have the two process declared concurrently in the same architecture (I might end up with a very long file and I don't like that they can theoretically access the same signals).

So I would really like to keep a "distinct files" approach but only for that specific process. Is there a way out of this or am I doomed?

Answer 1

This seems like an example where using multiple architectures of the same entity would help. You have a file along the lines of:

entity TestBench
end TestBench;

architecture SimpleTest of TestBench is
    -- You might have a component declaration for the UUT here
begin
    -- Test bench code here
end SimpleTest;

You can easily add another architecture. You can have architectures in separate files. You can also use direct entity instantiation to avoid the component declaration for the UUT (halving the work required if the UUT changes):

architecture AnotherTest of TestBench is
begin
    -- Test bench code here
    UUT : entity work.MyDesign (Behavioral)
    port map (
        -- Port map as usual
    ); 
end AnotherTest ;

This doesn't save having duplicate code, but at least it removes one of the port map lists.

Another point if you have a lot of signals in your UUT port map, is that this can be easier if you try to make more of the signals into vectors. For example, you might have lots of serial outputs of the same type going to different chips on the board. I have seen lots of people will name these like SPI_CS_SENSORS, SPI_CS_CPU, SPI_CS_FRONT_PANEL, etc. I find it makes the VHDL a lot more manageable if these are combined to SPI_CS (2 downto 0), with the mapping of what signal goes to what device specified by the circuit diagram. I suppose this is just preference, but maybe this sort of approach could help if you have really huge port lists.

Using a TestControl entity

A more sophisitcated approach would involve using a test control entity to implement all your stimulus. At the simplest level, this would have as ports all of the signals from the UUT you are interested in. A more sophisticated test bench would have a test control entity with interfaces that can control bus functional models that contain the actual pin wiggling required to exercise your design. You can have one file declaring this entity, say TestControl_Entity.vhd:

entity TestControl is
port (
    clk : out std_logic;
    UUTInput : out std_logic;
    UUTOutput : in std_logic
);

Then you have one or more architecture files, for example TestControl_SimpleTest.vhd:

architecture SimpleTest of TestControl is
begin
    -- Stimulus for simple test
end SimpleTest;

Your top level test bench would then look something like:

entity TestBench
end TestBench;

architecture Behavioral of TestBench is
    signal clk : std_logic;
    signal a : std_logic;
    signal b : std_logic;
begin

    -- Common processes like clock generation could go here

    UUT : entity work.MyDesign (Behavioral)
    port map (
        clk => clk,
        a => a,
        b => b
    ); 

    TestControl_inst : entity work.TestControl (SimpleTest)
    port map (
        clk => clk,
        UUTInput => a,
        UUTOutput => b
    ); 
end SimpleTest;

You can now change the test by changing the architecture selected for TestControl.

Using configurations

If you have a lot of different tests, you can use configurations to make it easier to select them. To do this, you first need to make the test control entity instantiation use a component declaration as opposed to direct instantiation. Then, at the end of each test control architecture file, create the configuration:

use work.all;

configuration Config_SimpleTest of TestBench is
    for Behavioral
        for TestControl_inst : TestControl
            use entity work.TestControl (TestControl_SimpleTest);
        end for;
    end for;
end Config_SimpleTest;

Now when you want to simulate, you simulate a configuration, so instead of a command like sim TestBench, you would run something like sim work.Config_SimpleTest. This makes it easier to manage test benches with a large number of different tests, because you don't have to edit any files in order to run them.

Answer 2

A generic can be added to the test bench entity, to control if simple or complex testing is done, like:

entity tb is
  generic(
    test : positive := 1);  -- 1: Simple, 2: Complex
end entity;


library ieee;
use ieee.std_logic_1164.all;

architecture syn of tb is
  -- Superset of declarations for simple and complex testing
begin

  simple_g : if test = 1 generate
    process is  -- Simple test process
    begin
      -- ... Simple testing
      wait;
    end process;
  end generate;

  complex_g : if test = 2 generate
    process is  -- Complex test process
    begin
      -- ... Complex testing
      wait;
    end process;
  end generate;

end architecture;

The drawback is that declarations can't be made conditional, so the declarations must be a superset of the signals and other controls for both simple and complex testing.

The simulator can control the generic value through options, for example -G for generic control in ModelSim simulator. It is thereby possible to compile once, and select simple or complex testing at runtime.