No feasible entries for infix operator "+"

Question

I am designing a 2s complement code but it is showing that error can any one help me with that.

library ieee;
use ieee.std_logic_1164.all;
use IEEE.std_logic_arith.all;

entity comp is
port(a : in std_logic_vector(7 downto 0);
    y : out std_logic_vector(7 downto 0));
end comp;

architecture dataflow of comp is
signal temp: std_logic;
begin
    y<=  not(a) + "00000001";
end dataflow;

Error: D:/modelsim_projects/2scmpliment.vhd(13): No feasible entries for infix operator "+".

Answer 1

When using Synopsys packages, you need to add use of the std_logic_unsigned package after std_logic_1164, like:

use IEEE.std_logic_unsigned.all;

With this you can even use integer notation for addition like:

y <= not(a) + 1;

Alternative is to use the IEEE VHDL standard numeric_std package, with changes like:

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
...
  y <= std_logic_vector(unsigned(not(a)) + 1);