I would like to get a list of signal names in a given design hierarchy from a Verilog design using vpi. It is a simple net name browser interface from my custom tool that is written in C and Python.
How can I get a list of signal names from a Verilog design and which VPI calls I should use to walk through the design?
Any info would be greatly appreciated.
In addition to the answer already given this code walk through your hierarchy and store design object of type
vpiLogic
you can adapt it to your needs. It stores the full names of the register in anunordered_map
which has nice O(1) access time during simulation.This code was developed for projects using both verilog and VHDL.
You'll also find that sometimes some IP's are protected which is handled gracefully, in addition the usage of scopes (
vpiInternalScope
) instead ofvpiModule
allows recursion insidegenerate
statements.It is c++ code but usage of
extern "C"
makes it callable from your EDA tools (tested using IUS).