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In Verilog Procedural Interface, is it possible to scan through iteration loop several times?

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#c #verilog #vpi
983
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How to add a new key to a Systemverilog associative array using VPI

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#system-verilog #vpi
1.5k
Views

How to check if a Systemverilog associative array has a key using VPI

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#system-verilog #vpi
565
Views

Pass an array element to vpi_handle_by_name

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#c++ #system-verilog #vpi
986
Views

Is it possible to call export function in VPI callback

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#system-verilog #system-verilog-assertions #system-verilog-dpi #vpi
272
Views

How to read memory value at a specific location using VPI and verilator?

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#verilog #simulation #system-verilog #verilator #vpi
297
Views

Is it possible to iterate systemverilog associative array with non-int index type through VPI c function?

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#system-verilog #associative-array #vpi
1.3k
Views

Reading array of regs using Verilator and VPI

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#verilog #verilator #vpi
145
Views

Time unit for VPI call back on signal value change

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#system-verilog #vpi
1.3k
Views

Obtaining signal names in the design (using VPI calls)

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#verilog #vpi
967
Views

How to get dimensions of a verilog vector port using PLI routines?

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#verilog #vpi
232
Views

Allocated structure for value_p to be used with VPI vpi_put_value()

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#verilog #system-verilog #vpi
1.2k
Views

Call task or function via VPI

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#verilog #system-verilog #vpi
307
Views

What API to use for a Verilator test harness?

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#c++ #verilog #systemc #verilator #vpi
1.2k
Views

SystemVerilog looping through hierarchy

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#c #system-verilog #vpi
1.2k
Views

SystemVerilog VPI release a callback handle after a vpiForceFlag

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#c #system-verilog #vpi
278
Views

Active direction of inout port during simulation using PLI

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#system-verilog #inout #vpi

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