Parameter passing in Systemverilog

Question

In the following Systemverilog code snippet:

xxx_model #    (.inst_name({inst_name,".ce_0"})) ce_0 (
...
..
);

I can't understand this part inst_name({inst_name,".ce_0"}). Kindly help me understand.

Answer 1

From your code snippet:

1. xxx_model is a parameterized module that takes a parameter of type string named inst_name.
2. you are instantiating this module and ce_0 is the name of the instance.
3. you are passing value {inst_name,".ce_0"} as the value of the parameter.

In this context Systemverilog will interpret curly braces as concatenation operator. inst_name in this line is probably a parameter being passed from the upper hierarchy. For the value for inst_name, kindly look for the instantiation of the enveloping module (the module one step upward in the module hierarchy).

Since inst_name is being used in a nested/recursive fashion here, the pattern in the code snippet seems to indicate that probably your code would have inst_name as a parameter in all the modules in the hierarchy. And the purpose is to have a reflection of the hierarchical name of the instance available as a string parameter.

With this scheme of recursive parameter passing, if your module hierarchy is foo->bar->frop->zoo, the parameter inst_name inside the lower most instance in the hierarchy zoo would have a value {inst_name, ".zoo"}. Here inst_name being passed from above would recursively evaluate to "foo.bar.frop**, and as a result the value of inst_name in the instantiation would be foo.bar.frop.zoo.