Put attributes into file possible?

Question

I am having a huge list of attributes being comprised of KEEP, DONT_TOUCH and MARK_DEBUG. It's mainly the list of signals I want to debug within my design. Since the list takes up so much space I was wondering if it's possible to somehow store all those attributes within a file and load them into my VHDL-design depending on a global constant-variable/signal/whatever?

So it would look something like this:

entity top is
end top ;
architecture Behavioral of top is
    if(DEBUG_ENABLE = "TRUE") then
        include "../path/to/file.txt";
    end if;
begin
end Behavioral;

and the file would look something like this:

attribute KEEP          : string;
attribute DONT_TOUCH    : string;
attribute MARK_DEBUG    : string;

attribute KEEP of signal_1            : signal is "TRUE";
attribute KEEP of signal_2            : signal is "TRUE";

attribute DONT_TOUCH of signal_1      : signal is "TRUE";
attribute DONT_TOUCH of signal_2      : signal is "TRUE";

attribute MARK_DEBUG of signal_1      : signal is "TRUE";
attribute MARK_DEBUG of signal_2      : signal is "TRUE";

Anyone knows, whether that is possible?

Cheers

EDIT: I don't mean to include libraries via use-statement. This is mainly for including other components or type/array/function/procedure-declarations into your entity. I want to include something into the architecture head which is not a component or similar which in the first place has no reference to my entity design, unless I explicitly instantiate it. I want to include something that describes the declared signals within my architecture head. As far as my understanding goes, this is not possible with libraries and packages.

Answer 1

You can implement conditional attributes like this:

attribute KEEP : BOOLEAN;

constant ENABLE_DEBUG : BOOLEAN := TRUE;
attribute KEEP of mySignal : signal is ENABLE_DEBUG;

Conditional string assignments can be solved by a ite (if-then-else) function.

function ite(cond : BOOLEAN; val1 : STRING ; val2 : STRING) return STRING is
begin
  if cond then
    return val1;
  else
    return val2;
  end if;
end function;

attribute FSM_ENCODING : STRING;
attribute FSM_ENCODING of State : signal is ite(ENABLE_DEBUG, "gray", "auto");

Some attributes can be loaded/assigned via vendor dependent constraint files.

Xilinx ISE example:
For example KEEP can be assigned in Schematic, VHDL and Verilog or via Xilinx XCF, NCF or UCF files. See Xilinx Constraint Guide for details on what attributes can be assigned where (Page 21) to which tool (synth. map, P&R, ...).

NET "myInstance/mySignal" KEEP;

Xilinx Vivado example:
Vivado supports the 'DONT_TOUCH' attribute, which can be set via XDC files. See Vivado's Using Constraints user guide for more details. The following example is from page 56:

set_property DONT_TOUCH true [get_cells fsm_reg]

So have a look into your synthesis tool's user guide and the list of supported attributes/constraints.