Just finished to read the RISCV spec, more specifically "Volume II: RISC-V Privileged Architectures" and have a question on how GDB (or any other debugger) is supposed to work.
Basically there are two ways to compile standard GDB: either hardware or Operating System based.
One difference is the "single step instruction" (si command) - for OS based, it is implemented on putting a software breakpoint (replacing the assembly instruction by a "breakpoint" assembly instruction) on each possible instruction which may follow (the next assembly instruction and possibly another one if current is a conditional branch). That ignores possible interrupts, page faults, operating system request, ...
For hardware based GDB, nothing is hidden so using software "breakpoint on next instruction" is not possible: there may be an interrupt or exception and GDB shall then stop at the entry of that handler.
If RISC-V is supposed to also support "user mode interrupt" it will have the same problem, in user mode executing "single assembly instruction step" may not know what is the next assembly instruction to replace and GDB-user may not want to skip/hide interrupt treatments.
Some "hardware" support is then needed to break on a hardware cycle counter, a bit like "real time register and its compare value register" for the timer.